Abstract
We have developed a fast programmable trigger processor board based on a field programmable gate array and a complex programmable logic device for use in the BELLE experiment. The trigger board accommodates 144 ECL input signals, 2 NIM input signals, 24 ECL output signals, and the VME bus specification. An asynchronous trigger logic for counting isolated clusters is used. We have obtained a trigger latency of 50 ns with full access to input and output signals via a VME interface. The trigger logic can be modified at any time depending on the experimental conditions.
Original language | English |
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Pages (from-to) | 634-639 |
Number of pages | 6 |
Journal | Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment |
Volume | 457 |
Issue number | 3 |
DOIs | |
State | Published - 21 Jan 2001 |