Ferroelectric memory design based on grounded-plate PMOS-gate cell architecture

Yeonbae Chung; Jung Hyun Kim; Jae Eun Yoon

doi:10.1109/EDSSC.2003.1283482

Ferroelectric memory design based on grounded-plate PMOS-gate cell architecture

Yeonbae Chung, Jung Hyun Kim, Jae Eun Yoon

School of Electronics Engineering

Kyungpook National University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper proposes a new FRAM design style based on grounded-plate PMOS-gate (GPPG) cell architecture. A GPPG cell consists of a PMOS access transistor and a ferroelectric capacitor. Its plate is grounded. The proposed scheme employs three novel operating methods: 1) V_DD precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore. Because this configuration doesn't need the on-pitch plate control circuitry, it is effective in realizing cost-effective chip sizes. Implementation for an experimental 2.5-V, 2-Mb FRAM prototype design in a 0.5-μm technology shows a cell array efficiency of 57 %, access time of 85 ns and an active current of 12 mA, respectively.

Original language	English
Title of host publication	2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	55-58
Number of pages	4
ISBN (Electronic)	0780377494, 9780780377493
DOIs	https://doi.org/10.1109/EDSSC.2003.1283482
State	Published - 2003
Event	IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 - Tsimshatsui, Kowloon, Hong Kong Duration: 16 Dec 2003 → 18 Dec 2003

Publication series

Name	2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003

Conference

Conference	IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
Country/Territory	Hong Kong
City	Tsimshatsui, Kowloon
Period	16/12/03 → 18/12/03

Access to Document

10.1109/EDSSC.2003.1283482

Cite this

Chung, Y., Kim, J. H., & Yoon, J. E. (2003). Ferroelectric memory design based on grounded-plate PMOS-gate cell architecture. In 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 (pp. 55-58). Article 1283482 (2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2003.1283482

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title = "Ferroelectric memory design based on grounded-plate PMOS-gate cell architecture",

abstract = "This paper proposes a new FRAM design style based on grounded-plate PMOS-gate (GPPG) cell architecture. A GPPG cell consists of a PMOS access transistor and a ferroelectric capacitor. Its plate is grounded. The proposed scheme employs three novel operating methods: 1) VDD precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore. Because this configuration doesn't need the on-pitch plate control circuitry, it is effective in realizing cost-effective chip sizes. Implementation for an experimental 2.5-V, 2-Mb FRAM prototype design in a 0.5-μm technology shows a cell array efficiency of 57 %, access time of 85 ns and an active current of 12 mA, respectively.",

author = "Yeonbae Chung and Kim, {Jung Hyun} and Yoon, {Jae Eun}",

note = "Publisher Copyright: {\textcopyright}2003 IEEE.; IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 ; Conference date: 16-12-2003 Through 18-12-2003",

year = "2003",

doi = "10.1109/EDSSC.2003.1283482",

language = "English",

series = "2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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booktitle = "2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003",

address = "United States",

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Chung, Y, Kim, JH & Yoon, JE 2003, Ferroelectric memory design based on grounded-plate PMOS-gate cell architecture. in 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003., 1283482, 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003, Institute of Electrical and Electronics Engineers Inc., pp. 55-58, IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003, Tsimshatsui, Kowloon, Hong Kong, 16/12/03. https://doi.org/10.1109/EDSSC.2003.1283482

Ferroelectric memory design based on grounded-plate PMOS-gate cell architecture. / Chung, Yeonbae; Kim, Jung Hyun; Yoon, Jae Eun.
2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003. Institute of Electrical and Electronics Engineers Inc., 2003. p. 55-58 1283482 (2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Chung, Yeonbae

AU - Kim, Jung Hyun

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N2 - This paper proposes a new FRAM design style based on grounded-plate PMOS-gate (GPPG) cell architecture. A GPPG cell consists of a PMOS access transistor and a ferroelectric capacitor. Its plate is grounded. The proposed scheme employs three novel operating methods: 1) VDD precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore. Because this configuration doesn't need the on-pitch plate control circuitry, it is effective in realizing cost-effective chip sizes. Implementation for an experimental 2.5-V, 2-Mb FRAM prototype design in a 0.5-μm technology shows a cell array efficiency of 57 %, access time of 85 ns and an active current of 12 mA, respectively.

AB - This paper proposes a new FRAM design style based on grounded-plate PMOS-gate (GPPG) cell architecture. A GPPG cell consists of a PMOS access transistor and a ferroelectric capacitor. Its plate is grounded. The proposed scheme employs three novel operating methods: 1) VDD precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore. Because this configuration doesn't need the on-pitch plate control circuitry, it is effective in realizing cost-effective chip sizes. Implementation for an experimental 2.5-V, 2-Mb FRAM prototype design in a 0.5-μm technology shows a cell array efficiency of 57 %, access time of 85 ns and an active current of 12 mA, respectively.

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M3 - Conference contribution

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T3 - 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003

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BT - 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003

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Chung Y, Kim JH, Yoon JE. Ferroelectric memory design based on grounded-plate PMOS-gate cell architecture. In 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003. Institute of Electrical and Electronics Engineers Inc. 2003. p. 55-58. 1283482. (2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003). doi: 10.1109/EDSSC.2003.1283482

Ferroelectric memory design based on grounded-plate PMOS-gate cell architecture

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