Fine-grain voltage tuned cache architecture for yield management under process variations

Joonho Kong; Yan Pan; Serkan Ozdemir; Anitha Mohan; Gokhan Memik; Sung Woo Chung

doi:10.1109/TVLSI.2011.2159634

Fine-grain voltage tuned cache architecture for yield management under process variations

Joonho Kong, Yan Pan, Serkan Ozdemir, Anitha Mohan, Gokhan Memik, Sung Woo Chung

School of Electronics Engineering

Research output: Contribution to journal › Article › peer-review

6 Scopus citations

Abstract

Process variations cause large fluctuations in performance and power consumption in the manufactured chips, which eventually results in yield losses. In this paper, to mitigate access time failures and excessive leakage in caches, we propose a novel selective wordline boosting mechanism combined with SRAM cell arrays voltage lowering. Based on our evaluation, the proposed approach recovers up to 83.1% of the yield losses.

Original language	English
Article number	5936660
Pages (from-to)	1532-1536
Number of pages	5
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	20
Issue number	8
DOIs	https://doi.org/10.1109/TVLSI.2011.2159634
State	Published - 2012

Keywords

Cache
process variation
selective wordline voltage boosting
supply voltage lowering
yield

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10.1109/TVLSI.2011.2159634

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abstract = "Process variations cause large fluctuations in performance and power consumption in the manufactured chips, which eventually results in yield losses. In this paper, to mitigate access time failures and excessive leakage in caches, we propose a novel selective wordline boosting mechanism combined with SRAM cell arrays voltage lowering. Based on our evaluation, the proposed approach recovers up to 83.1% of the yield losses.",

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AU - Chung, Sung Woo

PY - 2012

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KW - supply voltage lowering

KW - yield

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Fine-grain voltage tuned cache architecture for yield management under process variations

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Keywords

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