Five-step (Pad-pad short-pad open-short-open) de-embedding method and its verification

In Man Kang; Seung Jae Jung; Tae Hoon Choi; Jae Hong Jung; Chulho Chung; Han Su Kim; Hansu Oh; Hyun Woo Lee; Gwangdoo Jo; Young Kwang Kim; Han Gu Kim; Kyu Myung Choi

doi:10.1109/LED.2009.2013881

Five-step (Pad-pad short-pad open-short-open) de-embedding method and its verification

In Man Kang, Seung Jae Jung, Tae Hoon Choi, Jae Hong Jung, Chulho Chung, Han Su Kim, Hansu Oh, Hyun Woo Lee, Gwangdoo Jo, Young Kwang Kim, Han Gu Kim, Kyu Myung Choi

School of Electronics Engineering

Samsung

Research output: Contribution to journal › Article › peer-review

37 Scopus citations

Abstract

We present the method for five-step (pad-pad short-pad open-short-open) on-chip parasitic de-embedding. Its validation is verified by gate electrode resistance and input capacitance of transistors based on 45-nm CMOS process. Optimized dummy structures to remove the parasitic components due to the pad and routing metal are proposed. Parameters extracted by the proposed method have excellent physical and theoretical trends.

Original language	English
Pages (from-to)	398-400
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	30
Issue number	4
DOIs	https://doi.org/10.1109/LED.2009.2013881
State	Published - 2009

Keywords

Gate electrode resistance
Input capacitance
On-wafer RF measurement
Parasitic de-embedding
RF MOSFETs

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10.1109/LED.2009.2013881

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title = "Five-step (Pad-pad short-pad open-short-open) de-embedding method and its verification",

abstract = "We present the method for five-step (pad-pad short-pad open-short-open) on-chip parasitic de-embedding. Its validation is verified by gate electrode resistance and input capacitance of transistors based on 45-nm CMOS process. Optimized dummy structures to remove the parasitic components due to the pad and routing metal are proposed. Parameters extracted by the proposed method have excellent physical and theoretical trends.",

keywords = "Gate electrode resistance, Input capacitance, On-wafer RF measurement, Parasitic de-embedding, RF MOSFETs",

author = "Kang, {In Man} and Jung, {Seung Jae} and Choi, {Tae Hoon} and Jung, {Jae Hong} and Chulho Chung and Kim, {Han Su} and Hansu Oh and Lee, {Hyun Woo} and Gwangdoo Jo and Kim, {Young Kwang} and Kim, {Han Gu} and Choi, {Kyu Myung}",

year = "2009",

doi = "10.1109/LED.2009.2013881",

language = "English",

volume = "30",

pages = "398--400",

journal = "IEEE Electron Device Letters",

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publisher = "Institute of Electrical and Electronics Engineers Inc.",

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T1 - Five-step (Pad-pad short-pad open-short-open) de-embedding method and its verification

AU - Kang, In Man

AU - Jung, Seung Jae

AU - Choi, Tae Hoon

AU - Jung, Jae Hong

AU - Chung, Chulho

AU - Kim, Han Su

AU - Oh, Hansu

AU - Lee, Hyun Woo

AU - Jo, Gwangdoo

AU - Kim, Young Kwang

AU - Kim, Han Gu

AU - Choi, Kyu Myung

PY - 2009

Y1 - 2009

N2 - We present the method for five-step (pad-pad short-pad open-short-open) on-chip parasitic de-embedding. Its validation is verified by gate electrode resistance and input capacitance of transistors based on 45-nm CMOS process. Optimized dummy structures to remove the parasitic components due to the pad and routing metal are proposed. Parameters extracted by the proposed method have excellent physical and theoretical trends.

AB - We present the method for five-step (pad-pad short-pad open-short-open) on-chip parasitic de-embedding. Its validation is verified by gate electrode resistance and input capacitance of transistors based on 45-nm CMOS process. Optimized dummy structures to remove the parasitic components due to the pad and routing metal are proposed. Parameters extracted by the proposed method have excellent physical and theoretical trends.

KW - Gate electrode resistance

KW - Input capacitance

KW - On-wafer RF measurement

KW - Parasitic de-embedding

KW - RF MOSFETs

UR - http://www.scopus.com/inward/record.url?scp=67349104138&partnerID=8YFLogxK

U2 - 10.1109/LED.2009.2013881

DO - 10.1109/LED.2009.2013881

M3 - Article

AN - SCOPUS:67349104138

SN - 0741-3106

VL - 30

SP - 398

EP - 400

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 4

ER -

Five-step (Pad-pad short-pad open-short-open) de-embedding method and its verification

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Keywords

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