Floating gate memory based on MoS2 channel and iCVD polymer tunneling dielectric

Myung Hun Woo, Byung Chul Jang, Junhwan Choi, Gwang Hyuk Shin, Hyejeong Seong, Sung Gap Im, Sung Yool Choi

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

We investigated the floating gate memory based on MoS2 channel with metal nanoparticle charge trapping layer and polymer tunneling dielectric. Here, highly conformal and stable polymer insulator layer deposited via initiated chemical vapor deposition (iCVD) facilitates the fabricated floating gate memory to endure a substantial electrical stress significantly. To form a selective density and controllable distribution of charge trapping layer, different thickness of gold nanoparticles via thermal evaporation method was used. Al2O3 blocking dielectric is deposited via atomic layer deposition (ALD) process to increase gate coupling ratio for low power operation. The fabricated floating gate memory device exhibits tunable memory window with a high on/off ratio after applied programming and erasing pulse, allowing for multi-bit data storage with a long retention Ion/off ratio. All these results will be a foundation stone for the development of floating gate memory based on MoS2.

Original languageEnglish
Title of host publication2016 46th European Solid-State Device Research Conference, ESSDERC 2016
PublisherEditions Frontieres
Pages295-298
Number of pages4
ISBN (Electronic)9781509029693
DOIs
StatePublished - 18 Oct 2016
Event46th European Solid-State Device Research Conference, ESSDERC 2016 - Lausanne, Switzerland
Duration: 12 Sep 201615 Sep 2016

Publication series

NameEuropean Solid-State Device Research Conference
Volume2016-October
ISSN (Print)1930-8876

Conference

Conference46th European Solid-State Device Research Conference, ESSDERC 2016
Country/TerritorySwitzerland
CityLausanne
Period12/09/1615/09/16

Keywords

  • floating gate memory
  • initiated chemical vapoer deposition (iCVD)
  • MoS

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