FPGA Realization of the Observer-Based Sliding Discrete Fourier Transform

Discrete Fourier transform (DFT) is a widely used method of signal analysis in digital signal processing. The DFT converts a signal from time domain to frequency domain for further processing. For fixed-size sliding window applications of the DFT, the observer-based sliding DFT (oSDFT) algorithm has been shown to be stable, accurate, and theoretically faster, than the well-known block-oriented fast Fourier transforms (FFT). However, no hardware implementation of the oSDFT has been proposed yet. In this paper, a hardware optimized implementation of two variants of the algorithm for FPGA is presented. Such implementation is compared with the Xilinx FFT Intellectual Property in terms of processing speed and hardware requirements. The structure is implemented in Verilog HDL using Vivado IDE, with the aim of maximizing the processing speed and minimizing the required hardware resources. The analysis of the FPGA-based oSDFT and FFT circuits in a sample-by-sample processing scenario, reveals that the latency and energy usage of the oSDFT are smaller relative to the FFT. The latency and energy usage per sample processed of the implemented structures are up to 9 and 10 times lower than those of FFT respectively. The required resources for these methods are also presented and analyzed.