FRAM design style utilising bit-plate parallel cell architecture

Yeonbae Chung

doi:10.1049/el:20031104

FRAM design style utilising bit-plate parallel cell architecture

Yeonbae Chung

School of Electronics Engineering

Research output: Contribution to journal › Article › peer-review

2 Scopus citations

Abstract

A new FRAM design method utilising the bit-plate parallel cell architecture is presented. This method is effective in reducing circuit and layout overhead caused by on-pitch plate control circuitry. It also reduces the power consumption in memory array. Implementation results for a 0.13 μm, 512 kb FRAM prototype show that the memory block area in the proposed architecture is 15.6% less than that of the conventional structure.

Original language	English
Pages (from-to)	1706-1708
Number of pages	3
Journal	Electronics Letters
Volume	39
Issue number	24
DOIs	https://doi.org/10.1049/el:20031104
State	Published - 27 Nov 2003

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10.1049/el:20031104

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abstract = "A new FRAM design method utilising the bit-plate parallel cell architecture is presented. This method is effective in reducing circuit and layout overhead caused by on-pitch plate control circuitry. It also reduces the power consumption in memory array. Implementation results for a 0.13 μm, 512 kb FRAM prototype show that the memory block area in the proposed architecture is 15.6% less than that of the conventional structure.",

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AB - A new FRAM design method utilising the bit-plate parallel cell architecture is presented. This method is effective in reducing circuit and layout overhead caused by on-pitch plate control circuitry. It also reduces the power consumption in memory array. Implementation results for a 0.13 μm, 512 kb FRAM prototype show that the memory block area in the proposed architecture is 15.6% less than that of the conventional structure.

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JO - Electronics Letters

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FRAM design style utilising bit-plate parallel cell architecture

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