TY - JOUR
T1 - High performance ferroelectric memory with grounded-plate PMOS-gate cell technology
AU - Chung, Y.
PY - 2003/6
Y1 - 2003/6
N2 - A new FRAM architecture utilising a grounded-plate PMOS-gate (GPPG) ferroelectric cell is proposed. A GPPG cell consists of a PMOS access transistor and a ferroelectric data storage capacitor. Its plate is grounded. The proposed architecture employs three novel methods for cell operation: a VDD-precharged bit-line, a negative-voltage word-line technique and negative-pulse restoration. Because this configuration does not need the plate control circuitry, it greatly increases the memory cell efficiency. In addition, unlike other reported common-plate cells, this scheme can supply a sufficient voltage of VDD to the ferroelectric capacitor while detecting and storing the polarisation on the cell. Thus, there is no restriction on low-voltage operation. Furthermore, by employing a compact column-path circuitry which only activates the required 8-bit data, this architecture minimises the current consumption of the memory array. A 2.5-V, 2-Mbit prototype chip has been developed with 0.5-μm CMOS technology, and the possibility of the realisation of GPPG cell architecture has been confirmed.
AB - A new FRAM architecture utilising a grounded-plate PMOS-gate (GPPG) ferroelectric cell is proposed. A GPPG cell consists of a PMOS access transistor and a ferroelectric data storage capacitor. Its plate is grounded. The proposed architecture employs three novel methods for cell operation: a VDD-precharged bit-line, a negative-voltage word-line technique and negative-pulse restoration. Because this configuration does not need the plate control circuitry, it greatly increases the memory cell efficiency. In addition, unlike other reported common-plate cells, this scheme can supply a sufficient voltage of VDD to the ferroelectric capacitor while detecting and storing the polarisation on the cell. Thus, there is no restriction on low-voltage operation. Furthermore, by employing a compact column-path circuitry which only activates the required 8-bit data, this architecture minimises the current consumption of the memory array. A 2.5-V, 2-Mbit prototype chip has been developed with 0.5-μm CMOS technology, and the possibility of the realisation of GPPG cell architecture has been confirmed.
UR - http://www.scopus.com/inward/record.url?scp=0038487188&partnerID=8YFLogxK
U2 - 10.1049/ip-cds:20030351
DO - 10.1049/ip-cds:20030351
M3 - Article
AN - SCOPUS:0038487188
SN - 1350-2409
VL - 150
SP - 217
EP - 226
JO - IEE Proceedings: Circuits, Devices and Systems
JF - IEE Proceedings: Circuits, Devices and Systems
IS - 3
ER -