TY - JOUR
T1 - High performance fractional motion estimation in h.264/avc based on one-step algorithm and 8×4 element block processing
AU - Ta, Nam Thang
AU - Choi, Jun Rim
PY - 2011/2
Y1 - 2011/2
N2 - Conventional two-step algorithm, long latency of interpolation and various motion vectors are three factors that mainly induce high computation complexity of fractional motion estimation and also prevent it from encoding high-definition video. In order to overcome these obstacles, a high performance fractional motion engine is proposed in this paper with three techniques. First, based on high correlation between motion vector of a block and its up-layer as well as relationship of integer candidates, one-step algorithm is proposed. Second, an 8×4 element block processing is adopted, which not only eliminates almost redundancies in interpolation, but also still ensures hardware reusability. Finally, a scheme of processing 4×4 and 4×8 block with free of cycles is presented, so that the number of motion vectors can be reduced up to 59%. Experimental results show that the proposed design just needs 50% of gate count and 56% of cycles when compared with previous design while nearly maintaining the coding performance.
AB - Conventional two-step algorithm, long latency of interpolation and various motion vectors are three factors that mainly induce high computation complexity of fractional motion estimation and also prevent it from encoding high-definition video. In order to overcome these obstacles, a high performance fractional motion engine is proposed in this paper with three techniques. First, based on high correlation between motion vector of a block and its up-layer as well as relationship of integer candidates, one-step algorithm is proposed. Second, an 8×4 element block processing is adopted, which not only eliminates almost redundancies in interpolation, but also still ensures hardware reusability. Finally, a scheme of processing 4×4 and 4×8 block with free of cycles is presented, so that the number of motion vectors can be reduced up to 59%. Experimental results show that the proposed design just needs 50% of gate count and 56% of cycles when compared with previous design while nearly maintaining the coding performance.
KW - Fractional motion estimation
KW - h.264
KW - One-step
KW - Video signal processing
KW - VLSI
UR - http://www.scopus.com/inward/record.url?scp=79951944723&partnerID=8YFLogxK
U2 - 10.1016/j.image.2010.12.001
DO - 10.1016/j.image.2010.12.001
M3 - Article
AN - SCOPUS:79951944723
SN - 0923-5965
VL - 26
SP - 85
EP - 92
JO - Signal Processing: Image Communication
JF - Signal Processing: Image Communication
IS - 2
ER -