High performance parallelization of Boyer-Moore algorithm on many-core accelerators

Yosang Jeong, Myungho Lee, Dukyun Nam, Jik Soo Kim, Soonwook Hwang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Boyer-Moore (BM) algorithm is a single pattern string matching algorithm. It is considered as the most efficient string matching algorithm and used in many applications. The algorithm first calculates two string shift rules based on the given pattern string in the preprocessing phase. These rules help skip parts of the target input string where there is no match to be found. Using the two shift rules, pattern matching operations are performed against the target input sting in the second phase. The second phase is a time consuming process and needs to be parallelized to achieve the high performance string matching. In this paper, we parallelize the BM algorithm on the latest many core accelerators such as the Intel Xeon Phi and the Nvidia Tesla K20 GPU, along with the general-purpose multi-core processors. We partition the target input data amongst multiple threads for parallel execution. Data lying on the threads' boundaries need to be copied redundantly so that the pattern string lying on the boundary can be found. As the target length increases, the algorithm incurs increased matching operations. Also, as the pattern length increases, the number of possible matches decreases. This can potentially lead to the unbalanced workload distribution among threads. Furthermore, the redundant data copy significantly overloads the on-chip shared memories of the GPU for a large number of threads. We use the dynamic scheduling and the multithreading techniques to solve the load balancing problem. We also use the algorithmic cascading technique to reduce the burden on the shared memories of the GPU. Our parallel implementation leads to ∼ 17-times speedup on the Xeon Phi and ∼ 45-times speedup on the Nvidia Tesla K20GPU compared with a serial implementation on the host Intel Xeon processor.

Original languageEnglish
Title of host publicationProceedings - 2014 International Conference on Cloud and Autonomic Computing, ICCAC 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages265-272
Number of pages8
ISBN (Electronic)9781479958412
DOIs
StatePublished - 26 Jan 2015
Event2014 International Conference on Cloud and Autonomic Computing, ICCAC 2014 - London, United Kingdom
Duration: 8 Sep 201412 Sep 2014

Publication series

NameProceedings - 2014 International Conference on Cloud and Autonomic Computing, ICCAC 2014

Conference

Conference2014 International Conference on Cloud and Autonomic Computing, ICCAC 2014
Country/TerritoryUnited Kingdom
CityLondon
Period8/09/1412/09/14

Keywords

  • Algorithmic cascading
  • Boyer-Moore algorithm
  • dynamic scheduling
  • many-core accelerator
  • multithreading
  • parallelization

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