High-throughput PIM (Processing in-Memory) for DRAM using Bank-level Pipelined Architecture

Hyunsoo Lee; Hyundong Lee; Minseung Shin; Gyuri Shin; Sumin Jeon; Taigon Song

doi:10.1109/ISOCC59558.2023.10396302

High-throughput PIM (Processing in-Memory) for DRAM using Bank-level Pipelined Architecture

Hyunsoo Lee, Hyundong Lee, Minseung Shin, Gyuri Shin, Sumin Jeon, Taigon Song

School of Electronics Engineering

Kyungpook National University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Artificial intelligence (AI) is a technology requires massive computation. Among many solutions that accelerate AI for faster computation and low power, processing-in-memory (PIM) is a promising candidate. In this paper, we propose a PIM architecture of DRAM via custom pipelining. Our architecture proposes pipelining of operation units that leads to massive throughput, where an operation unit consists of eight banks. Our optimized pipelined architecture shows a -19.16% reduction in power-delay-product (PDP) per area and 24.1% better throughput compared to the latest DRAM PIM architecture with only 0.7% area overhead.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2023, ISOCC 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	101-102
Number of pages	2
ISBN (Electronic)	9798350327038
DOIs	https://doi.org/10.1109/ISOCC59558.2023.10396302
State	Published - 2023
Event	20th International SoC Design Conference, ISOCC 2023 - Jeju, Korea, Republic of Duration: 25 Oct 2023 → 28 Oct 2023

Publication series

Name	Proceedings - International SoC Design Conference 2023, ISOCC 2023

Conference

Conference	20th International SoC Design Conference, ISOCC 2023
Country/Territory	Korea, Republic of
City	Jeju
Period	25/10/23 → 28/10/23

Keywords

DRAM
Pipelining
processing in-memory (PIM)

Access to Document

10.1109/ISOCC59558.2023.10396302

Cite this

Lee, H., Lee, H., Shin, M., Shin, G., Jeon, S., & Song, T. (2023). High-throughput PIM (Processing in-Memory) for DRAM using Bank-level Pipelined Architecture. In Proceedings - International SoC Design Conference 2023, ISOCC 2023 (pp. 101-102). (Proceedings - International SoC Design Conference 2023, ISOCC 2023). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC59558.2023.10396302

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title = "High-throughput PIM (Processing in-Memory) for DRAM using Bank-level Pipelined Architecture",

abstract = "Artificial intelligence (AI) is a technology requires massive computation. Among many solutions that accelerate AI for faster computation and low power, processing-in-memory (PIM) is a promising candidate. In this paper, we propose a PIM architecture of DRAM via custom pipelining. Our architecture proposes pipelining of operation units that leads to massive throughput, where an operation unit consists of eight banks. Our optimized pipelined architecture shows a -19.16% reduction in power-delay-product (PDP) per area and 24.1% better throughput compared to the latest DRAM PIM architecture with only 0.7% area overhead.",

keywords = "DRAM, Pipelining, processing in-memory (PIM)",

author = "Hyunsoo Lee and Hyundong Lee and Minseung Shin and Gyuri Shin and Sumin Jeon and Taigon Song",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 20th International SoC Design Conference, ISOCC 2023 ; Conference date: 25-10-2023 Through 28-10-2023",

year = "2023",

doi = "10.1109/ISOCC59558.2023.10396302",

language = "English",

series = "Proceedings - International SoC Design Conference 2023, ISOCC 2023",

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Lee, H, Lee, H, Shin, M, Shin, G, Jeon, S & Song, T 2023, High-throughput PIM (Processing in-Memory) for DRAM using Bank-level Pipelined Architecture. in Proceedings - International SoC Design Conference 2023, ISOCC 2023. Proceedings - International SoC Design Conference 2023, ISOCC 2023, Institute of Electrical and Electronics Engineers Inc., pp. 101-102, 20th International SoC Design Conference, ISOCC 2023, Jeju, Korea, Republic of, 25/10/23. https://doi.org/10.1109/ISOCC59558.2023.10396302

High-throughput PIM (Processing in-Memory) for DRAM using Bank-level Pipelined Architecture. / Lee, Hyunsoo; Lee, Hyundong; Shin, Minseung et al.
Proceedings - International SoC Design Conference 2023, ISOCC 2023. Institute of Electrical and Electronics Engineers Inc., 2023. p. 101-102 (Proceedings - International SoC Design Conference 2023, ISOCC 2023).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Lee, Hyundong

AU - Shin, Minseung

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AU - Jeon, Sumin

AU - Song, Taigon

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Y1 - 2023

N2 - Artificial intelligence (AI) is a technology requires massive computation. Among many solutions that accelerate AI for faster computation and low power, processing-in-memory (PIM) is a promising candidate. In this paper, we propose a PIM architecture of DRAM via custom pipelining. Our architecture proposes pipelining of operation units that leads to massive throughput, where an operation unit consists of eight banks. Our optimized pipelined architecture shows a -19.16% reduction in power-delay-product (PDP) per area and 24.1% better throughput compared to the latest DRAM PIM architecture with only 0.7% area overhead.

AB - Artificial intelligence (AI) is a technology requires massive computation. Among many solutions that accelerate AI for faster computation and low power, processing-in-memory (PIM) is a promising candidate. In this paper, we propose a PIM architecture of DRAM via custom pipelining. Our architecture proposes pipelining of operation units that leads to massive throughput, where an operation unit consists of eight banks. Our optimized pipelined architecture shows a -19.16% reduction in power-delay-product (PDP) per area and 24.1% better throughput compared to the latest DRAM PIM architecture with only 0.7% area overhead.

KW - DRAM

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M3 - Conference contribution

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T3 - Proceedings - International SoC Design Conference 2023, ISOCC 2023

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BT - Proceedings - International SoC Design Conference 2023, ISOCC 2023

PB - Institute of Electrical and Electronics Engineers Inc.

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Lee H, Lee H, Shin M, Shin G, Jeon S, Song T. High-throughput PIM (Processing in-Memory) for DRAM using Bank-level Pipelined Architecture. In Proceedings - International SoC Design Conference 2023, ISOCC 2023. Institute of Electrical and Electronics Engineers Inc. 2023. p. 101-102. (Proceedings - International SoC Design Conference 2023, ISOCC 2023). doi: 10.1109/ISOCC59558.2023.10396302

High-throughput PIM (Processing in-Memory) for DRAM using Bank-level Pipelined Architecture

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