How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core

Moongon Jung; Taigon Song; Yang Wan; Young Joon Lee; Debabrata Mohapatra; Hong Wang; Greg Taylor; Devang Jariwala; Vijay Pitchumani; Patrick Morrow; Clair Webb; Paul Fischer; Sung Kyu Lim

doi:10.1109/CICC.2013.6658541

How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core

Moongon Jung, Taigon Song, Yang Wan, Young Joon Lee, Debabrata Mohapatra, Hong Wang, Greg Taylor, Devang Jariwala, Vijay Pitchumani, Patrick Morrow, Clair Webb, Paul Fischer, Sung Kyu Lim

School of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

18 Scopus citations

Abstract

Low power is considered by many as the driving force for 3D ICs, yet there have been few thorough design studies on how to reduce power in 3D ICs. In this paper, we discuss design methodologies to reduce power consumption in 3D IC designs using a commercial-grade CPU core (OpenSPARC T2 core). To demonstrate power benefits in 3D ICs, four design techniques are explored: (1) 3D floorplanning, (2) metal layer usage control for intra-block-level routing, (3) dual-Vth design, and (4) functional unit block (FUB) folding. With aforementioned methods combined, our 2-tier 3D designs provide up to 52.3% reduced footprint, 25.5% shorter wirelength, 30.2% decreased buffer cell count, and 21.2% power reduction over the 2D counterpart under the same performance.

Original language	English
Title of host publication	Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	9781467361460
DOIs	https://doi.org/10.1109/CICC.2013.6658541
State	Published - 7 Nov 2013
Event	35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013 - San Jose, CA, United States Duration: 22 Sep 2013 → 25 Sep 2013

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
ISSN (Print)	0886-5930

Conference

Conference	35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013
Country/Territory	United States
City	San Jose, CA
Period	22/09/13 → 25/09/13

Access to Document

10.1109/CICC.2013.6658541

Cite this

Jung, M., Song, T., Wan, Y., Lee, Y. J., Mohapatra, D., Wang, H., Taylor, G., Jariwala, D., Pitchumani, V., Morrow, P., Webb, C., Fischer, P., & Lim, S. K. (2013). How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core. In Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013 Article 6658541 (Proceedings of the Custom Integrated Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2013.6658541

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title = "How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core",

abstract = "Low power is considered by many as the driving force for 3D ICs, yet there have been few thorough design studies on how to reduce power in 3D ICs. In this paper, we discuss design methodologies to reduce power consumption in 3D IC designs using a commercial-grade CPU core (OpenSPARC T2 core). To demonstrate power benefits in 3D ICs, four design techniques are explored: (1) 3D floorplanning, (2) metal layer usage control for intra-block-level routing, (3) dual-Vth design, and (4) functional unit block (FUB) folding. With aforementioned methods combined, our 2-tier 3D designs provide up to 52.3% reduced footprint, 25.5% shorter wirelength, 30.2% decreased buffer cell count, and 21.2% power reduction over the 2D counterpart under the same performance.",

author = "Moongon Jung and Taigon Song and Yang Wan and Lee, {Young Joon} and Debabrata Mohapatra and Hong Wang and Greg Taylor and Devang Jariwala and Vijay Pitchumani and Patrick Morrow and Clair Webb and Paul Fischer and Lim, {Sung Kyu}",

year = "2013",

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doi = "10.1109/CICC.2013.6658541",

language = "English",

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series = "Proceedings of the Custom Integrated Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013",

address = "United States",

note = "35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013 ; Conference date: 22-09-2013 Through 25-09-2013",

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Jung, M, Song, T, Wan, Y, Lee, YJ, Mohapatra, D, Wang, H, Taylor, G, Jariwala, D, Pitchumani, V, Morrow, P, Webb, C, Fischer, P & Lim, SK 2013, How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core. in Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013., 6658541, Proceedings of the Custom Integrated Circuits Conference, Institute of Electrical and Electronics Engineers Inc., 35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013, San Jose, CA, United States, 22/09/13. https://doi.org/10.1109/CICC.2013.6658541

How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core. / Jung, Moongon; Song, Taigon; Wan, Yang et al.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013. Institute of Electrical and Electronics Engineers Inc., 2013. 6658541 (Proceedings of the Custom Integrated Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T2 - 35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013

AU - Jung, Moongon

AU - Song, Taigon

AU - Wan, Yang

AU - Lee, Young Joon

AU - Mohapatra, Debabrata

AU - Wang, Hong

AU - Taylor, Greg

AU - Jariwala, Devang

AU - Pitchumani, Vijay

AU - Morrow, Patrick

AU - Webb, Clair

AU - Fischer, Paul

AU - Lim, Sung Kyu

PY - 2013/11/7

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N2 - Low power is considered by many as the driving force for 3D ICs, yet there have been few thorough design studies on how to reduce power in 3D ICs. In this paper, we discuss design methodologies to reduce power consumption in 3D IC designs using a commercial-grade CPU core (OpenSPARC T2 core). To demonstrate power benefits in 3D ICs, four design techniques are explored: (1) 3D floorplanning, (2) metal layer usage control for intra-block-level routing, (3) dual-Vth design, and (4) functional unit block (FUB) folding. With aforementioned methods combined, our 2-tier 3D designs provide up to 52.3% reduced footprint, 25.5% shorter wirelength, 30.2% decreased buffer cell count, and 21.2% power reduction over the 2D counterpart under the same performance.

AB - Low power is considered by many as the driving force for 3D ICs, yet there have been few thorough design studies on how to reduce power in 3D ICs. In this paper, we discuss design methodologies to reduce power consumption in 3D IC designs using a commercial-grade CPU core (OpenSPARC T2 core). To demonstrate power benefits in 3D ICs, four design techniques are explored: (1) 3D floorplanning, (2) metal layer usage control for intra-block-level routing, (3) dual-Vth design, and (4) functional unit block (FUB) folding. With aforementioned methods combined, our 2-tier 3D designs provide up to 52.3% reduced footprint, 25.5% shorter wirelength, 30.2% decreased buffer cell count, and 21.2% power reduction over the 2D counterpart under the same performance.

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ER -

Jung M, Song T, Wan Y, Lee YJ, Mohapatra D, Wang H et al. How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core. In Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013. Institute of Electrical and Electronics Engineers Inc. 2013. 6658541. (Proceedings of the Custom Integrated Circuits Conference). doi: 10.1109/CICC.2013.6658541

How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core

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