TY - JOUR
T1 - Impact of H2 High-Pressure Annealing onto InGaAs Quantum-Well Metal-Oxide-Semiconductor Field-Effect Transistors with Al2O3/HfO2 Gate-Stack
AU - Kim, Tae Woo
AU - Kwon, Hyuk Min
AU - Shin, Seung Heon
AU - Shin, Chan Soo
AU - Park, Won Kyu
AU - Chiu, Eddie
AU - Rivera, Manny
AU - Lew, Jae Ik
AU - Veksler, Dmitry
AU - Orzali, Tommaso
AU - Kim, Dae Hyun
N1 - Publisher Copyright:
© 1980-2012 IEEE.
PY - 2015/7/1
Y1 - 2015/7/1
N2 - We report on the impact of H2 high-pressure annealing (HPA) onto In0.7Ga0.3As MOSCAPs and quantum-well (QW) MOSFETs with Al2O3/HfO2 gate-stack. After HPA with process condition of 300 °C, H2 ambient and pressure of 20 atm, we observed notable improvements of the capacitance-voltage (CV) characteristics in InGaAs MOSCAPs with Al2O3/HfO2 gate-stack, such as reduction of equivalent-oxide-thickness and less frequency dispersion in the accumulation region. There was 20% improvement of the interfacial trap density ( D-{{\rm {it}}}). Then, we incorporated the HPA process into the fabrication of sub-100-nm In0.7Ga0.3As QW MOSFETs, to investigate the impact of HPA process. After HPA process, the device with L-{g} = 50 nm exhibits improved subthreshold-swing (SS) = 105 mV/decade, in comparison with SS = 130 mV/decade for the reference device without HPA process. Finally, we carried out reliability assessment under a constant-voltage-stress (CVS), and it turns out that the HPA process was effective in mitigating a shift of threshold voltage ( \Delta \text{V}-{T}) during the CVS. These are attributed to the effective passivation of oxide traps in the high- k dielectric layer and interfacial traps, after HPA process in the H2 ambient.
AB - We report on the impact of H2 high-pressure annealing (HPA) onto In0.7Ga0.3As MOSCAPs and quantum-well (QW) MOSFETs with Al2O3/HfO2 gate-stack. After HPA with process condition of 300 °C, H2 ambient and pressure of 20 atm, we observed notable improvements of the capacitance-voltage (CV) characteristics in InGaAs MOSCAPs with Al2O3/HfO2 gate-stack, such as reduction of equivalent-oxide-thickness and less frequency dispersion in the accumulation region. There was 20% improvement of the interfacial trap density ( D-{{\rm {it}}}). Then, we incorporated the HPA process into the fabrication of sub-100-nm In0.7Ga0.3As QW MOSFETs, to investigate the impact of HPA process. After HPA process, the device with L-{g} = 50 nm exhibits improved subthreshold-swing (SS) = 105 mV/decade, in comparison with SS = 130 mV/decade for the reference device without HPA process. Finally, we carried out reliability assessment under a constant-voltage-stress (CVS), and it turns out that the HPA process was effective in mitigating a shift of threshold voltage ( \Delta \text{V}-{T}) during the CVS. These are attributed to the effective passivation of oxide traps in the high- k dielectric layer and interfacial traps, after HPA process in the H2 ambient.
KW - atomic layer deposition (ALD)
KW - high-pressure annealing
KW - In0.53Ga0.47As MOSFET
KW - interfacial trap density (Dit)
KW - subthreshold-swing (SS)
UR - http://www.scopus.com/inward/record.url?scp=84934276160&partnerID=8YFLogxK
U2 - 10.1109/LED.2015.2438433
DO - 10.1109/LED.2015.2438433
M3 - Article
AN - SCOPUS:84934276160
SN - 0741-3106
VL - 36
SP - 672
EP - 674
JO - IEEE Electron Device Letters
JF - IEEE Electron Device Letters
IS - 7
M1 - 7114237
ER -