Impact of lateral engineering on the logic performance of Sub-50 nm InGaAs HEMTs

We have studied the combined impact of side-recess length and the gate length on the logic performance of sub-100 nm InGaAs HEMTs. We have found that increasing L_side significantly improves the short-channel effects and the logic performance of the device. Our experimental work confirms that lateral engineering at the drain side is essential for improving the electrostatic integrity of sub-100 nm gate length InGaAs HEMTs. The trade-off of widening L_side is the increase of R_s. With further device optimization in the form of reduced gate leakage current, selfaligned ohmic contacts and the development of a high performance p-channel device, InGaAs-based FETs could well be the technology of choice when the Si CMOS roadmap comes to end.