Implementation of a cycle-based simulator for the design of a processor core

Moon Gyung Rim; Byung In Moon; Sang Jun An; Dong Ryul Ryu; Yong Surk Lee

doi:10.1109/APASIC.1999.824040

Implementation of a cycle-based simulator for the design of a processor core

Moon Gyung Rim, Byung In Moon, Sang Jun An, Dong Ryul Ryu, Yong Surk Lee

Yonsei University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

This paper presents an approach to establish and simulate a DSP core by using a cycle-based simulator written in C language. The simulator is written with information of a target DSP core. Instructions are analyzed in order to determine which blocks are used. Then, appropriate control signals are applied to the blocks. The implemented simulator can give the cycle-based information such as changes of control signals and register flags that are not given by instruction-based simulators. After modeling and validating the simulator it is used to verify the HDL model of target DSP core and to enhance its performance as well as to develop applications for the core.

Original language	English
Title of host publication	AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	108-110
Number of pages	3
ISBN (Print)	0780357051, 9780780357051
DOIs	https://doi.org/10.1109/APASIC.1999.824040
State	Published - 1999
Event	1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 - Seoul, Korea, Republic of Duration: 23 Aug 1999 → 25 Aug 1999

Publication series

Name	AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Conference

Conference	1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999
Country/Territory	Korea, Republic of
City	Seoul
Period	23/08/99 → 25/08/99

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10.1109/APASIC.1999.824040

Cite this

Rim, M. G., Moon, B. I., An, S. J., Ryu, D. R., & Lee, Y. S. (1999). Implementation of a cycle-based simulator for the design of a processor core. In AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs (pp. 108-110). Article 824040 (AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APASIC.1999.824040

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title = "Implementation of a cycle-based simulator for the design of a processor core",

abstract = "This paper presents an approach to establish and simulate a DSP core by using a cycle-based simulator written in C language. The simulator is written with information of a target DSP core. Instructions are analyzed in order to determine which blocks are used. Then, appropriate control signals are applied to the blocks. The implemented simulator can give the cycle-based information such as changes of control signals and register flags that are not given by instruction-based simulators. After modeling and validating the simulator it is used to verify the HDL model of target DSP core and to enhance its performance as well as to develop applications for the core.",

author = "Rim, {Moon Gyung} and Moon, {Byung In} and An, {Sang Jun} and Ryu, {Dong Ryul} and Lee, {Yong Surk}",

note = "Publisher Copyright: {\textcopyright} 1999 IEEE.; 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 ; Conference date: 23-08-1999 Through 25-08-1999",

year = "1999",

doi = "10.1109/APASIC.1999.824040",

language = "English",

isbn = "0780357051",

series = "AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "108--110",

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address = "United States",

}

Rim, MG, Moon, BI, An, SJ, Ryu, DR & Lee, YS 1999, Implementation of a cycle-based simulator for the design of a processor core. in AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs., 824040, AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs, Institute of Electrical and Electronics Engineers Inc., pp. 108-110, 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999, Seoul, Korea, Republic of, 23/08/99. https://doi.org/10.1109/APASIC.1999.824040

Implementation of a cycle-based simulator for the design of a processor core. / Rim, Moon Gyung; Moon, Byung In; An, Sang Jun et al.
AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs. Institute of Electrical and Electronics Engineers Inc., 1999. p. 108-110 824040 (AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Implementation of a cycle-based simulator for the design of a processor core

AU - Rim, Moon Gyung

AU - Moon, Byung In

AU - An, Sang Jun

AU - Ryu, Dong Ryul

AU - Lee, Yong Surk

PY - 1999

Y1 - 1999

N2 - This paper presents an approach to establish and simulate a DSP core by using a cycle-based simulator written in C language. The simulator is written with information of a target DSP core. Instructions are analyzed in order to determine which blocks are used. Then, appropriate control signals are applied to the blocks. The implemented simulator can give the cycle-based information such as changes of control signals and register flags that are not given by instruction-based simulators. After modeling and validating the simulator it is used to verify the HDL model of target DSP core and to enhance its performance as well as to develop applications for the core.

AB - This paper presents an approach to establish and simulate a DSP core by using a cycle-based simulator written in C language. The simulator is written with information of a target DSP core. Instructions are analyzed in order to determine which blocks are used. Then, appropriate control signals are applied to the blocks. The implemented simulator can give the cycle-based information such as changes of control signals and register flags that are not given by instruction-based simulators. After modeling and validating the simulator it is used to verify the HDL model of target DSP core and to enhance its performance as well as to develop applications for the core.

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U2 - 10.1109/APASIC.1999.824040

DO - 10.1109/APASIC.1999.824040

M3 - Conference contribution

AN - SCOPUS:46249125468

SN - 0780357051

SN - 9780780357051

T3 - AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

SP - 108

EP - 110

BT - AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999

Y2 - 23 August 1999 through 25 August 1999

ER -

Implementation of a cycle-based simulator for the design of a processor core

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