Abstract
BACKGROUND AND OBJECTIVE: Recently, with the increase in the population of hearing impaired people, various types of hearing aids have been rapidly developed. In particular, a fully implantable middle ear hearing device (F-IMEHD) is developed for people with sensorineural hearing loss. The F-IMEHD system comprises an implantable microphone, a transducer, and a signal processor. The signal processor should have a small size and consume less power for implantation in a human body. METHODS: In this study, we designed and fabricated a signal-processing chip using the modified FFT algorithm. This algorithm was developed focusing on eliminating time delay and system complexity in the transform process. The designed signal-processing chip comprises a 4-channel WDRC, a fitting memory, a communication 1control part, and a pulse density modulator. Each channel is separated using a 64-point fast Fourier transform (FFT) method and the gain value is matched using the fitting table in the fitting memory. RESULTS AND CONCLUSION: The chip was designed by Verilog-HDL and the designed HDL codes were verified by Modelsim-PE 10.3 (Mentor graphics, USA). The chip was fabricated using a 0.18 µm CMOS process (SMIC, China). Experiments were performed on a cadaver to verify the performance of the fabricated chip.
Original language | English |
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Pages (from-to) | S399-S413 |
Journal | Technology and Health Care |
Volume | 29 |
Issue number | S1 |
DOIs | |
State | Published - 2021 |
Keywords
- CMOS process
- Cadaver experiment
- Fully implantable middle ear hearing device
- Verilog-HDL
- wide dynamic range