Implementation of a low-cost phase-locked loop clock-recovery module for 40-Gb/s optical receivers

Dong Sik Woo, Kang Wook Kim, Sang Kyu Lim, Jesoo Ko

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

A low-cost, compact, high-performance clock-recovery (CR) module using a new phase-locked loop (PLL) for 40-Gb/s optical receivers is successfully designed and implemented. The newly implemented frequency detector in the PLL helps to reduce the current consumption and also extended the frequency-capture range. The implemented PLL clock-recovery module demonstrates advantages over the conventional open-loop type clock-recovery module with a DR filter by significantly improving clock jitter, thus reducing overall module cost, and allowing the possibility of providing a proper clock signal in the case of temporary loss of NRZ input signals. The CR module exhibits error-free operation during a 30-min BER test with a time-division-multiplexing (TDM) 40-Gb/s transmission system.

Original languageEnglish
Pages (from-to)312-315
Number of pages4
JournalMicrowave and Optical Technology Letters
Volume48
Issue number2
DOIs
StatePublished - Feb 2006

Keywords

  • 40 Gb/s; phase-locked loop (PLL)
  • Clock and data recovery (CDR)
  • Clock recovery (CR)
  • Jitter

Fingerprint

Dive into the research topics of 'Implementation of a low-cost phase-locked loop clock-recovery module for 40-Gb/s optical receivers'. Together they form a unique fingerprint.

Cite this