@inproceedings{ff48853f47704b52bca4ae5ae00bc071,
title = "Implementation of a phase-locked loop clock recovery module for 40 Gb/s optical receivers",
abstract = "A low-cost, high-performance clock recovery (CR) module using a phase-locked loop (PLL) for 40 Gb/s optical receivers have been successfully designed and implemented. The recovered 40 GHz clock is synchronized with a stable 10 GHz VC-DRO. The timing jitter of the implemented PLL clock recovery module is significantly reduced as compared with the conventional open-loop type clock recovery module with a DR filter. The measured RMS jitter with the phase-locked CR module is about 250 fs. In addition, the CR module has been operated error-free during a 30-minute BER test with 40 Gb/s optical transceivers.",
keywords = "40 Gb/s, Clock Recovery, Phase-Locked Loop (PLL), Timing Jitter",
author = "Park, \{Chan Ho\} and Woo, \{Dong Sik\} and Kim, \{Tae Gyu\} and Lim, \{Sang Kyu\} and Kim, \{Kang Wook\}",
year = "2005",
doi = "10.1109/MWSYM.2005.1517168",
language = "English",
isbn = "0780388461",
series = "IEEE MTT-S International Microwave Symposium Digest",
pages = "2127--2130",
booktitle = "2005 IEEE MTT-S International Microwave Symposium Digest",
note = "2005 IEEE MTT-S International Microwave Symposium ; Conference date: 12-06-2005 Through 17-06-2005",
}