Implementation of low-voltage static RAM with enhanced data stability and circuit speed

Yeonbae Chung, Seung Ho Song

Research output: Contribution to journalArticlepeer-review

27 Scopus citations

Abstract

This paper presents a novel SRAM circuit technique for simultaneously enhancing the cell operating margin and improving the circuit speed in low-voltage operation. During each access, the wordline and cell power node of selected SRAM cells are internally boosted into two different voltage levels. This technique with optimized boosting levels expands the read margin and the write margin to a sufficient amount without an increase of cell size. It also improves the SRAM circuit speed owing to an increase of the cell read-out current. A 256 Kbit SRAM test chip with the proposed technique has been fabricated in a 0.18 μm CMOS logic process. For 0.8 V supply voltage, the design scheme increases the cell read margin by 76%, the cell write margin by 54% and the cell read-out current by three times at the expense of 14.6% additional active power. Silicon measurement eventually confirms that the proposed SRAM achieves nearly 1.2 orders of magnitude reduction in a die bit-error count while operating with 26% faster speed compared with those of conventional SRAM.

Original languageEnglish
Pages (from-to)944-951
Number of pages8
JournalMicroelectronics Journal
Volume40
Issue number6
DOIs
StatePublished - Jun 2009

Keywords

  • Cell current
  • Six-transistor cell
  • SRAM
  • Static noise margin
  • Write margin

Fingerprint

Dive into the research topics of 'Implementation of low-voltage static RAM with enhanced data stability and circuit speed'. Together they form a unique fingerprint.

Cite this