@inproceedings{4385f942713348c0bebf4168805ff578,
title = "Integration challenges for high-performance carbon nanotube logic",
abstract = "As the scaling of silicon-based devices becomes more challenging, alternative channel materials are being actively explored. One approach is to replace the silicon channel with nanoparticles - for example, carbon nanotubes - that offer higher performance and better scaling potential. However, the incorporation of nanoparticles requires the development of new 'bottom up' fabrication techniques to grow or place particles at precise locations on a substrate. The inherent randomness of these assembly processes has an obvious impact on device yield, which must be taken into account in optimizing the layout of a device. Here we describe a simple statistical analysis of device yield that can give insight into the self-assembly process, and is particularly useful for characterizing nanoparticle self-assembly from solution.",
keywords = "carbon nanotubes, nanoparticles, placement, self assembly",
author = "Hannon, {James B.} and Hongsik Park and Tulevski, {George S.} and Wilfried Haensch",
note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 2014 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, BCTM 2014 ; Conference date: 28-09-2014 Through 01-10-2014",
year = "2014",
month = dec,
day = "9",
doi = "10.1109/BCTM.2014.6981298",
language = "English",
series = "Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "123--127",
booktitle = "2014 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, BCTM 2014",
address = "United States",
}