I/O power estimation and analysis of high-speed channels in Through-Silicon Via (TSV)-based 3D IC

Joohee Kim; Jonghyun Cho; Jun So Pak; Taigon Song; Joungho Kim; Hyungdong Lee; Junho Lee; Kunwoo Park

doi:10.1109/EPEPS.2010.5642539

I/O power estimation and analysis of high-speed channels in Through-Silicon Via (TSV)-based 3D IC

Joohee Kim, Jonghyun Cho, Jun So Pak, Taigon Song, Joungho Kim, Hyungdong Lee, Junho Lee, Kunwoo Park

School of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

23 Scopus citations

Abstract

In today's integrated circuits, power consumption has become the most important factor, and must be seriously investigated among the various performance metrics. In this study, power estimations for various through-silicon via (TSV)-based three-dimensional integrated circuit (3D IC) designs were conducted in efforts to realize low-power-consumption 3D IC. In addition, the dominant power-consuming factor was found among the TSV-based interconnect components by a power comparison analysis based on the proposed model.

Original language	English
Title of host publication	2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010
Publisher	IEEE Computer Society
Pages	41-44
Number of pages	4
ISBN (Print)	9781424468652
DOIs	https://doi.org/10.1109/EPEPS.2010.5642539
State	Published - 2010

Publication series

Name	2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010

Keywords

Dynamic power consumption
Interposer
Re-distribution layer (RDL)
Three-dimensional integrated circuit (3D IC)
Through-Silicon Via (TSV)

Access to Document

10.1109/EPEPS.2010.5642539

Cite this

Kim, J., Cho, J., Pak, J. S., Song, T., Kim, J., Lee, H., Lee, J., & Park, K. (2010). I/O power estimation and analysis of high-speed channels in Through-Silicon Via (TSV)-based 3D IC. In 2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010 (pp. 41-44). Article 5642539 (2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010). IEEE Computer Society. https://doi.org/10.1109/EPEPS.2010.5642539

Kim, Joohee ; Cho, Jonghyun ; Pak, Jun So et al. / I/O power estimation and analysis of high-speed channels in Through-Silicon Via (TSV)-based 3D IC. 2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010. IEEE Computer Society, 2010. pp. 41-44 (2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010).

@inproceedings{b451b5c848eb4f35a4de9a3e4b7eaa05,

title = "I/O power estimation and analysis of high-speed channels in Through-Silicon Via (TSV)-based 3D IC",

abstract = "In today's integrated circuits, power consumption has become the most important factor, and must be seriously investigated among the various performance metrics. In this study, power estimations for various through-silicon via (TSV)-based three-dimensional integrated circuit (3D IC) designs were conducted in efforts to realize low-power-consumption 3D IC. In addition, the dominant power-consuming factor was found among the TSV-based interconnect components by a power comparison analysis based on the proposed model.",

keywords = "Dynamic power consumption, Interposer, Re-distribution layer (RDL), Three-dimensional integrated circuit (3D IC), Through-Silicon Via (TSV)",

author = "Joohee Kim and Jonghyun Cho and Pak, {Jun So} and Taigon Song and Joungho Kim and Hyungdong Lee and Junho Lee and Kunwoo Park",

year = "2010",

doi = "10.1109/EPEPS.2010.5642539",

language = "English",

isbn = "9781424468652",

series = "2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010",

publisher = "IEEE Computer Society",

pages = "41--44",

booktitle = "2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010",

address = "United States",

}

Kim, J, Cho, J, Pak, JS, Song, T, Kim, J, Lee, H, Lee, J & Park, K 2010, I/O power estimation and analysis of high-speed channels in Through-Silicon Via (TSV)-based 3D IC. in 2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010., 5642539, 2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010, IEEE Computer Society, pp. 41-44. https://doi.org/10.1109/EPEPS.2010.5642539

I/O power estimation and analysis of high-speed channels in Through-Silicon Via (TSV)-based 3D IC. / Kim, Joohee; Cho, Jonghyun; Pak, Jun So et al.
2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010. IEEE Computer Society, 2010. p. 41-44 5642539 (2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - I/O power estimation and analysis of high-speed channels in Through-Silicon Via (TSV)-based 3D IC

AU - Kim, Joohee

AU - Cho, Jonghyun

AU - Pak, Jun So

AU - Song, Taigon

AU - Kim, Joungho

AU - Lee, Hyungdong

AU - Lee, Junho

AU - Park, Kunwoo

PY - 2010

Y1 - 2010

N2 - In today's integrated circuits, power consumption has become the most important factor, and must be seriously investigated among the various performance metrics. In this study, power estimations for various through-silicon via (TSV)-based three-dimensional integrated circuit (3D IC) designs were conducted in efforts to realize low-power-consumption 3D IC. In addition, the dominant power-consuming factor was found among the TSV-based interconnect components by a power comparison analysis based on the proposed model.

AB - In today's integrated circuits, power consumption has become the most important factor, and must be seriously investigated among the various performance metrics. In this study, power estimations for various through-silicon via (TSV)-based three-dimensional integrated circuit (3D IC) designs were conducted in efforts to realize low-power-consumption 3D IC. In addition, the dominant power-consuming factor was found among the TSV-based interconnect components by a power comparison analysis based on the proposed model.

KW - Dynamic power consumption

KW - Interposer

KW - Re-distribution layer (RDL)

KW - Three-dimensional integrated circuit (3D IC)

KW - Through-Silicon Via (TSV)

UR - http://www.scopus.com/inward/record.url?scp=78650952214&partnerID=8YFLogxK

U2 - 10.1109/EPEPS.2010.5642539

DO - 10.1109/EPEPS.2010.5642539

M3 - Conference contribution

AN - SCOPUS:78650952214

SN - 9781424468652

T3 - 2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010

SP - 41

EP - 44

BT - 2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010

PB - IEEE Computer Society

ER -

Kim J, Cho J, Pak JS, Song T, Kim J, Lee H et al. I/O power estimation and analysis of high-speed channels in Through-Silicon Via (TSV)-based 3D IC. In 2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010. IEEE Computer Society. 2010. p. 41-44. 5642539. (2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010). doi: 10.1109/EPEPS.2010.5642539

I/O power estimation and analysis of high-speed channels in Through-Silicon Via (TSV)-based 3D IC

Abstract

Publication series

Keywords

Access to Document

Other files and links

Fingerprint

Cite this