Lightweighted Shallow CTS Techniques for Checking Clock Tree Synthesizable Paths and Optimizing Clock Tree in RTL Design Time

The microcontroller unit (MCU) are mainly used in low power devices, which use limited energy sources such as batteries, energy harvesting, and wireless communications. Therefore, reducing the operating power of the MCU is important to improve energy efficiency by extending battery life or minimizing energy consumption. The MCU is one of the chip designs composed of digital integrated circuits. The clock signal is important element to the MCU. The clock tree, which consists of the clock signal, is directly related to MCU low power operation and performance improvement. Also, chip verification process is important role to improve performance of overall system and reliability to the MCU. However, as the degree of integation of chips, the chip verification process increases complexity and time-comsumption to process many data. Currently, many users dependent on licensed electronic design automation (EDA) tools to ensure high accuracy, minimizing errors in circuit design and improving reliability. The use of licensed EDA tool puts a burden on users including high costs, limited license, difficulty in customization, slow speed, etc. An effective approach to avoid problems by using licensed EDA tools proceeds verification that is unrestricted license and customization for possible using only a register transfer level (RTL) source. In this paper, we propose to predict roughly pre-estimated CTS results using an RTL source in which temporary logic using random buffer insertion is placed before the route process. This paper contributes to reducing MCU operating power and hardware area by performing optimized CTS and minimizing resources according to the RTL structure to be designed.