Logic suitability of 50-nm In_0.7Ga_0.3As HEMTs for beyond-CMOS applications

We have experimentally studied the suitability of nanometer-scale In_0.7Ga_0.3As high-electron mobility transistors (HEMTs) as an n-channel device for a future high-speed and low-power logic technology for beyond-CMOS applications. To this end, we have fabricated 50- to 150-nm-gate-length In_0.7Ga_0.3As HEMTs with different gate stack designs. This has allowed us to investigate the role of Schottky barrier height (Φ_B) and insulator thickness t_Ins on the logic characteristics of In_0.7Ga_0.3As HEMTs. The best 50-nm HEMTs with the highest Φ_B and the smallest trm ins exhibit an I_ON/I_OFF ratio in excess of 10⁴ and a subthreshold slope (S) below 86 mV/dec. These nonoptimized 50-nm In_0.7Ga_0.3As HEMTs also show a logic gate delay CV/ I of around 1 ps at a supply voltage of 0.5 V, while maintaining an I_ONI_OFF ratio above 10⁴, which is comparable to state-of-the-art Si MOSFETs. As one of the alternatives for beyond-CMOS technologies, we believe that InAs-rich InGaAs HEMTs hold a considerable promise.