TY - GEN
T1 - Low bandwidth fractional motion estimation in H.264 design for mobile devices
AU - Kim, Jeong Hoon
AU - Choi, Jun Rim
PY - 2011
Y1 - 2011
N2 - The conventional fractional motion estimation(FME) approach needs a two-step interpolation for half-pel and quarter-pel refinements. Though two-sequential-step brings high encoding performance, it introduces a huge computational load and memory bandwidth requirement for searching seventeen fractional points for each of the forty-one motion vectors. These obstacles become more difficult when running the applications on mobile device with the limitation of power and hardware resource. In this paper, a low bandwidth FME design is proposed with two techniques. Based on high correlation between motion vector of a block and its up-layer as well as relationship of integer candidates, one-step FME algorithm is proposed to reduce computation complexity and memory bandwidth requirement. In addition, a memory saving scheme is proposed while carefully considering the trade-off between hardware resource and memory saving. Experimental results show that the proposed design just needs 66% of gate counts and saves 88% of memory bandwidth when compared with previous design.
AB - The conventional fractional motion estimation(FME) approach needs a two-step interpolation for half-pel and quarter-pel refinements. Though two-sequential-step brings high encoding performance, it introduces a huge computational load and memory bandwidth requirement for searching seventeen fractional points for each of the forty-one motion vectors. These obstacles become more difficult when running the applications on mobile device with the limitation of power and hardware resource. In this paper, a low bandwidth FME design is proposed with two techniques. Based on high correlation between motion vector of a block and its up-layer as well as relationship of integer candidates, one-step FME algorithm is proposed to reduce computation complexity and memory bandwidth requirement. In addition, a memory saving scheme is proposed while carefully considering the trade-off between hardware resource and memory saving. Experimental results show that the proposed design just needs 66% of gate counts and saves 88% of memory bandwidth when compared with previous design.
UR - http://www.scopus.com/inward/record.url?scp=80053636653&partnerID=8YFLogxK
U2 - 10.1109/MWSCAS.2011.6026289
DO - 10.1109/MWSCAS.2011.6026289
M3 - Conference contribution
AN - SCOPUS:80053636653
SN - 9781612848570
T3 - Midwest Symposium on Circuits and Systems
BT - 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
T2 - 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
Y2 - 7 August 2011 through 10 August 2011
ER -