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Low complexity semi–systolic multiplication architecture over GF(2m)

  • Kyungpook National University

Research output: Contribution to journalArticlepeer-review

8 Scopus citations

Abstract

This paper presents a semi-systolic Montgomery multiplier based on the redundant basis representation of the finite field elements. The proposed multiplier has less hardware and time complexities compared to related multipliers. We also propose a serial systolic Montgomery multiplier that can be applied well in space-limited hardware. Furthermore, a simple inversion based on the proposed scheme is presented.

Original languageEnglish
Article number20140713
JournalIEICE Electronics Express
Volume11
Issue number20
DOIs
StatePublished - 3 Oct 2014

Keywords

  • Finite field arithmetic
  • Modular multiplication
  • Systolic array

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