TY - GEN
T1 - Low-cost application-aware DVFS for multi-core architecture
AU - Kong, Joonho
AU - Choi, Jinhang
AU - Choi, Lynn
AU - Chung, Sung Woo
PY - 2008
Y1 - 2008
N2 - As technology scales down, energy/power consumption in the microprocessor has become a serious problem. Especially, as the industry moves on to multi-core processor systems, energy/power management in multi-core systems has become more and more important. In this paper, we propose new DVFS technique in multi-core systems. Our proposed technique finds the optimal DVFS level using Energy-Delay Product (EDP) and Energy-Delay2 Product (ED2 P), which considers energy-efficiency of computation. According to determined DVFS level, the voltage and frequency of processor cores are changed. In our evaluations, our proposed technique shows 5.6% and 54.3% EDP reduction compared to the energy-biased and performance-biased scheme, respectively. In case of ED2 P, our proposed technique reduces 36.4% and 14.7% of ED 2P compared to the energy-biased and performance-biased scheme, respectively. The proposed technique can be a good alternative in future multi-core system where the both energy/power consumption and performance are critical.
AB - As technology scales down, energy/power consumption in the microprocessor has become a serious problem. Especially, as the industry moves on to multi-core processor systems, energy/power management in multi-core systems has become more and more important. In this paper, we propose new DVFS technique in multi-core systems. Our proposed technique finds the optimal DVFS level using Energy-Delay Product (EDP) and Energy-Delay2 Product (ED2 P), which considers energy-efficiency of computation. According to determined DVFS level, the voltage and frequency of processor cores are changed. In our evaluations, our proposed technique shows 5.6% and 54.3% EDP reduction compared to the energy-biased and performance-biased scheme, respectively. In case of ED2 P, our proposed technique reduces 36.4% and 14.7% of ED 2P compared to the energy-biased and performance-biased scheme, respectively. The proposed technique can be a good alternative in future multi-core system where the both energy/power consumption and performance are critical.
UR - http://www.scopus.com/inward/record.url?scp=57849124109&partnerID=8YFLogxK
U2 - 10.1109/ICCIT.2008.124
DO - 10.1109/ICCIT.2008.124
M3 - Conference contribution
AN - SCOPUS:57849124109
SN - 9780769534077
T3 - Proceedings - 3rd International Conference on Convergence and Hybrid Information Technology, ICCIT 2008
SP - 106
EP - 111
BT - Proceedings - 3rd International Conference on Convergence and Hybrid Information Technology, ICCIT 2008
T2 - 3rd International Conference on Convergence and Hybrid Information Technology, ICCIT 2008
Y2 - 11 November 2008 through 13 November 2008
ER -
