@inproceedings{4bcf2f67b64646b0830f721059fb5ab2,
title = "Low-cost Hardware Architecture for Integral Image Generation using Word Length Reduction",
abstract = "An integral image is widely used in face detection to calculate feature values at high speed. However, implementing integral images in hardware requires considerable logic and memory resources. This paper proposes a hardware architecture for integral image generation with reduced resource usage by applying the word length reduction method. When implemented in an FPGA, the proposed architecture uses about 83% fewer Slice LUTs than the conventional integral image method. Therefore, the proposed architecture is suitable for low-cost realtime face detection systems.",
keywords = "face detection, FPGA, hardware architecture, integral image",
author = "Junghwan Kim and Jongkil Hyun and Byungin Moon",
note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 17th International System-on-Chip Design Conference, ISOCC 2020 ; Conference date: 21-10-2020 Through 24-10-2020",
year = "2020",
month = oct,
day = "21",
doi = "10.1109/ISOCC50952.2020.9332974",
language = "English",
series = "Proceedings - International SoC Design Conference, ISOCC 2020",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "119--120",
booktitle = "Proceedings - International SoC Design Conference, ISOCC 2020",
address = "United States",
}