Low-cost Hardware Architecture for Integral Image Generation using Word Length Reduction

Junghwan Kim, Jongkil Hyun, Byungin Moon

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

An integral image is widely used in face detection to calculate feature values at high speed. However, implementing integral images in hardware requires considerable logic and memory resources. This paper proposes a hardware architecture for integral image generation with reduced resource usage by applying the word length reduction method. When implemented in an FPGA, the proposed architecture uses about 83% fewer Slice LUTs than the conventional integral image method. Therefore, the proposed architecture is suitable for low-cost realtime face detection systems.

Original languageEnglish
Title of host publicationProceedings - International SoC Design Conference, ISOCC 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages119-120
Number of pages2
ISBN (Electronic)9781728183312
DOIs
StatePublished - 21 Oct 2020
Event17th International System-on-Chip Design Conference, ISOCC 2020 - Yeosu, Korea, Republic of
Duration: 21 Oct 202024 Oct 2020

Publication series

NameProceedings - International SoC Design Conference, ISOCC 2020

Conference

Conference17th International System-on-Chip Design Conference, ISOCC 2020
Country/TerritoryKorea, Republic of
CityYeosu
Period21/10/2024/10/20

Keywords

  • face detection
  • FPGA
  • hardware architecture
  • integral image

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