Low-Power 4-Trit Current-Steering DAC for Ternary Data Conversion

Youngchang Choi; Sunmean Kim; Seunghan Baek; Seokhyeong Kang

doi:10.1109/ISOCC50952.2020.9332983

Low-Power 4-Trit Current-Steering DAC for Ternary Data Conversion

Youngchang Choi, Sunmean Kim, Seunghan Baek, Seokhyeong Kang

School of Electronics Engineering

Pohang University of Science and Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

A current-steering ternary DAC is proposed to reduce the power consumption and size while retaining better resolution than conventional binary DACs. By applying the method proposed in this paper, a 4-Trit ternary DAC is designed. It operates at 100MHz sampling rate and 1.8V supply voltage, and is implemented in 180nm CMOS technology. Compared to 6-bit binary DAC [5], it reduces power consumption by 31.69% to 30.64 %, and reduces area by 75.48 %.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference, ISOCC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	254-255
Number of pages	2
ISBN (Electronic)	9781728183312
DOIs	https://doi.org/10.1109/ISOCC50952.2020.9332983
State	Published - 21 Oct 2020
Event	17th International System-on-Chip Design Conference, ISOCC 2020 - Yeosu, Korea, Republic of Duration: 21 Oct 2020 → 24 Oct 2020

Publication series

Name	Proceedings - International SoC Design Conference, ISOCC 2020

Conference

Conference	17th International System-on-Chip Design Conference, ISOCC 2020
Country/Territory	Korea, Republic of
City	Yeosu
Period	21/10/20 → 24/10/20

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10.1109/ISOCC50952.2020.9332983

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Choi, Y., Kim, S., Baek, S., & Kang, S. (2020). Low-Power 4-Trit Current-Steering DAC for Ternary Data Conversion. In Proceedings - International SoC Design Conference, ISOCC 2020 (pp. 254-255). Article 9332983 (Proceedings - International SoC Design Conference, ISOCC 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC50952.2020.9332983

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title = "Low-Power 4-Trit Current-Steering DAC for Ternary Data Conversion",

abstract = "A current-steering ternary DAC is proposed to reduce the power consumption and size while retaining better resolution than conventional binary DACs. By applying the method proposed in this paper, a 4-Trit ternary DAC is designed. It operates at 100MHz sampling rate and 1.8V supply voltage, and is implemented in 180nm CMOS technology. Compared to 6-bit binary DAC [5], it reduces power consumption by 31.69\% to 30.64 \%, and reduces area by 75.48 \%.",

author = "Youngchang Choi and Sunmean Kim and Seunghan Baek and Seokhyeong Kang",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 17th International System-on-Chip Design Conference, ISOCC 2020 ; Conference date: 21-10-2020 Through 24-10-2020",

year = "2020",

month = oct,

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doi = "10.1109/ISOCC50952.2020.9332983",

language = "English",

series = "Proceedings - International SoC Design Conference, ISOCC 2020",

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Choi, Y, Kim, S, Baek, S & Kang, S 2020, Low-Power 4-Trit Current-Steering DAC for Ternary Data Conversion. in Proceedings - International SoC Design Conference, ISOCC 2020., 9332983, Proceedings - International SoC Design Conference, ISOCC 2020, Institute of Electrical and Electronics Engineers Inc., pp. 254-255, 17th International System-on-Chip Design Conference, ISOCC 2020, Yeosu, Korea, Republic of, 21/10/20. https://doi.org/10.1109/ISOCC50952.2020.9332983

Low-Power 4-Trit Current-Steering DAC for Ternary Data Conversion. / Choi, Youngchang; Kim, Sunmean; Baek, Seunghan et al.
Proceedings - International SoC Design Conference, ISOCC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 254-255 9332983 (Proceedings - International SoC Design Conference, ISOCC 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Baek, Seunghan

AU - Kang, Seokhyeong

PY - 2020/10/21

Y1 - 2020/10/21

N2 - A current-steering ternary DAC is proposed to reduce the power consumption and size while retaining better resolution than conventional binary DACs. By applying the method proposed in this paper, a 4-Trit ternary DAC is designed. It operates at 100MHz sampling rate and 1.8V supply voltage, and is implemented in 180nm CMOS technology. Compared to 6-bit binary DAC [5], it reduces power consumption by 31.69% to 30.64 %, and reduces area by 75.48 %.

AB - A current-steering ternary DAC is proposed to reduce the power consumption and size while retaining better resolution than conventional binary DACs. By applying the method proposed in this paper, a 4-Trit ternary DAC is designed. It operates at 100MHz sampling rate and 1.8V supply voltage, and is implemented in 180nm CMOS technology. Compared to 6-bit binary DAC [5], it reduces power consumption by 31.69% to 30.64 %, and reduces area by 75.48 %.

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BT - Proceedings - International SoC Design Conference, ISOCC 2020

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 17th International System-on-Chip Design Conference, ISOCC 2020

Y2 - 21 October 2020 through 24 October 2020

ER -

Low-Power 4-Trit Current-Steering DAC for Ternary Data Conversion

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