Low-power accessless SRAM macro in logic CMOS technology

Jae Ho Ryu; Weijie Cheng; Yong Woon Kim; Jeong Wook Cho; Yeonbae Chung

doi:10.1109/ICSICT.2010.5667844

Low-power accessless SRAM macro in logic CMOS technology

Jae Ho Ryu, Weijie Cheng, Yong Woon Kim, Jeong Wook Cho, Yeonbae Chung

School of Electronics Engineering

Kyungpook National University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, a novel low-power SRAM based on 4-transistor (4T) latch cell is described. The memory cells are composed of two cross-coupled inverters without access transistors. The sources of PMOS transistors are connected to bitlines while the sources of NMOS transistors are connected to wordlines. They are accessed by totally new read and write method which results in low operating power dissipation in the nature. A 1.8 V SRAM test chip has been fabricated in a 0.18 μm CMOS technology, which demonstrated the functionality of the memory cell. This new SRAM operates with 30 % reduction in read power and 42 % reduction in write power compared to the conventional 6-transistor (6T) SRAM.

Original language	English
Title of host publication	ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings
Pages	90-92
Number of pages	3
DOIs	https://doi.org/10.1109/ICSICT.2010.5667844
State	Published - 2010
Event	2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology - Shanghai, China Duration: 1 Nov 2010 → 4 Nov 2010

Publication series

Name	ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Conference

Conference	2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology
Country/Territory	China
City	Shanghai
Period	1/11/10 → 4/11/10

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10.1109/ICSICT.2010.5667844

Cite this

Ryu, J. H., Cheng, W., Kim, Y. W., Cho, J. W., & Chung, Y. (2010). Low-power accessless SRAM macro in logic CMOS technology. In ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings (pp. 90-92). Article 5667844 (ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings). https://doi.org/10.1109/ICSICT.2010.5667844

@inproceedings{217ab08e46df4ff3b8f247ec9b353d56,

title = "Low-power accessless SRAM macro in logic CMOS technology",

abstract = "In this paper, a novel low-power SRAM based on 4-transistor (4T) latch cell is described. The memory cells are composed of two cross-coupled inverters without access transistors. The sources of PMOS transistors are connected to bitlines while the sources of NMOS transistors are connected to wordlines. They are accessed by totally new read and write method which results in low operating power dissipation in the nature. A 1.8 V SRAM test chip has been fabricated in a 0.18 μm CMOS technology, which demonstrated the functionality of the memory cell. This new SRAM operates with 30 % reduction in read power and 42 % reduction in write power compared to the conventional 6-transistor (6T) SRAM.",

author = "Ryu, {Jae Ho} and Weijie Cheng and Kim, {Yong Woon} and Cho, {Jeong Wook} and Yeonbae Chung",

year = "2010",

doi = "10.1109/ICSICT.2010.5667844",

language = "English",

isbn = "9781424457984",

series = "ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings",

pages = "90--92",

booktitle = "ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings",

note = "2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology ; Conference date: 01-11-2010 Through 04-11-2010",

}

Ryu, JH, Cheng, W, Kim, YW, Cho, JW & Chung, Y 2010, Low-power accessless SRAM macro in logic CMOS technology. in ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings., 5667844, ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings, pp. 90-92, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Shanghai, China, 1/11/10. https://doi.org/10.1109/ICSICT.2010.5667844

Low-power accessless SRAM macro in logic CMOS technology. / Ryu, Jae Ho; Cheng, Weijie; Kim, Yong Woon et al.
ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2010. p. 90-92 5667844 (ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - In this paper, a novel low-power SRAM based on 4-transistor (4T) latch cell is described. The memory cells are composed of two cross-coupled inverters without access transistors. The sources of PMOS transistors are connected to bitlines while the sources of NMOS transistors are connected to wordlines. They are accessed by totally new read and write method which results in low operating power dissipation in the nature. A 1.8 V SRAM test chip has been fabricated in a 0.18 μm CMOS technology, which demonstrated the functionality of the memory cell. This new SRAM operates with 30 % reduction in read power and 42 % reduction in write power compared to the conventional 6-transistor (6T) SRAM.

AB - In this paper, a novel low-power SRAM based on 4-transistor (4T) latch cell is described. The memory cells are composed of two cross-coupled inverters without access transistors. The sources of PMOS transistors are connected to bitlines while the sources of NMOS transistors are connected to wordlines. They are accessed by totally new read and write method which results in low operating power dissipation in the nature. A 1.8 V SRAM test chip has been fabricated in a 0.18 μm CMOS technology, which demonstrated the functionality of the memory cell. This new SRAM operates with 30 % reduction in read power and 42 % reduction in write power compared to the conventional 6-transistor (6T) SRAM.

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Ryu JH, Cheng W, Kim YW, Cho JW, Chung Y. Low-power accessless SRAM macro in logic CMOS technology. In ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2010. p. 90-92. 5667844. (ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings). doi: 10.1109/ICSICT.2010.5667844

Low-power accessless SRAM macro in logic CMOS technology

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