Low-power high-throughput deblocking filter architecture for H.264/AVC

The paper proposes an efficient deblocking filter architecture for H.264/AVC. A four-stage pipeline has been adopted to boost the speed of deblocking filter process up to 192 clock cycles per one macroblock. Hybrid edge filter order enhances the reusability of intermediate data which not only increases system throughput, but also reduces power consumption because of diminishing memory access times. In addition, for saving power purpose, our architecture utilizes the buffers instead of SRAM on-chip for storing temporary data. Experimental results show that our design can achieve the throughput of 1146kMB/s while saving up to 25% power consumption when compared with previous design. The architecture is implemented in 0.18μm standard cell library, consumes 26.01 K gates at a clock frequency of 220MHz.