Low-Power Ternary Multiplication Using Approximate Computing

Sunmean Kim, Yesung Kang, Seunghan Baek, Youngchang Choi, Seokhyeong Kang

Research output: Contribution to journalArticlepeer-review

21 Scopus citations

Abstract

We propose a novel approximate computing technique for low-power ternary multiplication. A carry-truncated ternary multiplier, error compensation circuits, and 2×2 ternary multipliers with various accuracies are proposed using the low-power design methodology with carbon nanotube FETs. An accuracy-configurable design method is proposed to design energy-efficient 6×6 approximate ternary multipliers. The energy benefit of the proposed 6×6 approximate ternary multipliers have been verified using HSPICE simulation. The proposed approximate design shows 82.8% power-delay product with 41.8% mean absolute percentage error improvement over the previous approximate multiplier-based design. Image processing applications are conducted using the proposed approximate designs to confirm that the accuracy of ternary multiplication is satisfied the user's requirement.

Original languageEnglish
Article number9387404
Pages (from-to)2947-2951
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume68
Issue number8
DOIs
StatePublished - Aug 2021

Keywords

  • approximate computing
  • CNTFET
  • Multi-valued Logic
  • ternary Logic Circuits
  • ternary multiplier

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