Lg= 60 nm In0.53Ga0.47As MBCFETs: From gm-max= 13.7 mS/μm and Q = 180 to virtual-source modeling

J. H. Yoo; H. B. Jo; I. G. Lee; S. M. Choi; J. M. Baek; S. T. Lee; H. Jang; M. W. Kong; H. H. Kim; H. J. Lee; H. J. Kim; H. S. Jeong; W. S. Park; D. H. Ko; S. H. Shin; H. M. Kwon; S. K. Kim; J. G. Kim; J. Yun; T. Kim; K. Y. Shin; T. W. Kim; J. K. Shin; J. H. Lee; C. S. Shin; K. S. Seo; D. H. Kim

doi:10.23919/VLSITechnologyandCir57934.2023.10185250

L_g= 60 nm In_0.53Ga_0.47As MBCFETs: From g_m-max= 13.7 mS/μm and Q = 180 to virtual-source modeling

J. H. Yoo
, H. B. Jo
, I. G. Lee
, S. M. Choi
, J. M. Baek
, S. T. Lee
, H. Jang
, M. W. Kong
, H. H. Kim
, H. J. Lee
, H. J. Kim
, H. S. Jeong
, W. S. Park
, D. H. Ko
, S. H. Shin
, H. M. Kwon
, S. K. Kim
, J. G. Kim
, J. Yun
, T. Kim

K. Y. Shin, T. W. Kim, J. K. Shin, J. H. Lee, C. S. Shin, K. S. Seo, D. H. Kim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

In this paper, we report scalable 5 -level stacked gate-all-around (GAA) In 0.53 Ga0.47As multi-bridge channel FETs (MBCFETs), with careful attention paid to fluorine migration. At its heart, we maintained temperature of all the unit process steps below 300 °C and inserted an n-InP ledge into a top In0.52Al0.48As sacrificial layer to suppress F- -induced donor passivation. In addition, we used a selectively regrown n+In0.53Ga0.47 As contact formation by MOCVD and precision dry etching. The dry etching process resulted in a highly vertical etching slope along both the S/D and Wg directions. The fabricated Lg=60nm MBCFET showed a record combination of S=76mV/dec, gm-max=13.7 mS/mum, ION=2.24mA/mum and Q=180 at VDS=0.5V.

Original language	English
Title of host publication	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9784863488069
DOIs	https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185250
State	Published - 2023
Event	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 - Kyoto, Japan Duration: 11 Jun 2023 → 16 Jun 2023

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2023-June
ISSN (Print)	0743-1562

Conference

Conference	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
Country/Territory	Japan
City	Kyoto
Period	11/06/23 → 16/06/23

Access to Document

10.23919/VLSITechnologyandCir57934.2023.10185250

Cite this

Yoo, J. H., Jo, H. B., Lee, I. G., Choi, S. M., Baek, J. M., Lee, S. T., Jang, H., Kong, M. W., Kim, H. H., Lee, H. J., Kim, H. J., Jeong, H. S., Park, W. S., Ko, D. H., Shin, S. H., Kwon, H. M., Kim, S. K., Kim, J. G., Yun, J., ... Kim, D. H. (2023). L_g= 60 nm In_0.53Ga_0.47As MBCFETs: From g_m-max= 13.7 mS/μm and Q = 180 to virtual-source modeling. In 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2023-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185250

@inproceedings{dda8c3b9cf7d4dd8990942b86b97c108,

title = "Lg= 60 nm In0.53Ga0.47As MBCFETs: From gm-max= 13.7 mS/μm and Q = 180 to virtual-source modeling",

abstract = "In this paper, we report scalable 5 -level stacked gate-all-around (GAA) In 0.53 Ga0.47As multi-bridge channel FETs (MBCFETs), with careful attention paid to fluorine migration. At its heart, we maintained temperature of all the unit process steps below 300 °C and inserted an n-InP ledge into a top In0.52Al0.48As sacrificial layer to suppress F- -induced donor passivation. In addition, we used a selectively regrown n+In0.53Ga0.47 As contact formation by MOCVD and precision dry etching. The dry etching process resulted in a highly vertical etching slope along both the S/D and Wg directions. The fabricated Lg=60nm MBCFET showed a record combination of S=76mV/dec, gm-max=13.7 mS/mum, ION=2.24mA/mum and Q=180 at VDS=0.5V.",

author = "Yoo, \{J. H.\} and Jo, \{H. B.\} and Lee, \{I. G.\} and Choi, \{S. M.\} and Baek, \{J. M.\} and Lee, \{S. T.\} and H. Jang and Kong, \{M. W.\} and Kim, \{H. H.\} and Lee, \{H. J.\} and Kim, \{H. J.\} and Jeong, \{H. S.\} and Park, \{W. S.\} and Ko, \{D. H.\} and Shin, \{S. H.\} and Kwon, \{H. M.\} and Kim, \{S. K.\} and Kim, \{J. G.\} and J. Yun and T. Kim and Shin, \{K. Y.\} and Kim, \{T. W.\} and Shin, \{J. K.\} and Lee, \{J. H.\} and Shin, \{C. S.\} and Seo, \{K. S.\} and Kim, \{D. H.\}",

note = "Publisher Copyright: {\textcopyright} 2023 JSAP.; 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 ; Conference date: 11-06-2023 Through 16-06-2023",

year = "2023",

doi = "10.23919/VLSITechnologyandCir57934.2023.10185250",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023",

address = "United States",

}

Yoo, JH, Jo, HB, Lee, IG, Choi, SM, Baek, JM, Lee, ST, Jang, H, Kong, MW, Kim, HH, Lee, HJ, Kim, HJ, Jeong, HS, Park, WS, Ko, DH, Shin, SH, Kwon, HM, Kim, SK, Kim, JG, Yun, J, Kim, T, Shin, KY, Kim, TW, Shin, JK, Lee, JH, Shin, CS, Seo, KS & Kim, DH 2023, L_g= 60 nm In_0.53Ga_0.47As MBCFETs: From g_m-max= 13.7 mS/μm and Q = 180 to virtual-source modeling. in 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Digest of Technical Papers - Symposium on VLSI Technology, vol. 2023-June, Institute of Electrical and Electronics Engineers Inc., 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023, Kyoto, Japan, 11/06/23. https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185250

L_g= 60 nm In_0.53Ga_0.47As MBCFETs: From g_m-max= 13.7 mS/μm and Q = 180 to virtual-source modeling. / Yoo, J. H.; Jo, H. B.; Lee, I. G. et al.
2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2023-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Lg= 60 nm In0.53Ga0.47As MBCFETs

T2 - 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023

AU - Yoo, J. H.

AU - Jo, H. B.

AU - Lee, I. G.

AU - Choi, S. M.

AU - Baek, J. M.

AU - Lee, S. T.

AU - Jang, H.

AU - Kong, M. W.

AU - Kim, H. H.

AU - Lee, H. J.

AU - Kim, H. J.

AU - Jeong, H. S.

AU - Park, W. S.

AU - Ko, D. H.

AU - Shin, S. H.

AU - Kwon, H. M.

AU - Kim, S. K.

AU - Kim, J. G.

AU - Yun, J.

AU - Kim, T.

AU - Shin, K. Y.

AU - Kim, T. W.

AU - Shin, J. K.

AU - Lee, J. H.

AU - Shin, C. S.

AU - Seo, K. S.

AU - Kim, D. H.

PY - 2023

Y1 - 2023

N2 - In this paper, we report scalable 5 -level stacked gate-all-around (GAA) In 0.53 Ga0.47As multi-bridge channel FETs (MBCFETs), with careful attention paid to fluorine migration. At its heart, we maintained temperature of all the unit process steps below 300 °C and inserted an n-InP ledge into a top In0.52Al0.48As sacrificial layer to suppress F- -induced donor passivation. In addition, we used a selectively regrown n+In0.53Ga0.47 As contact formation by MOCVD and precision dry etching. The dry etching process resulted in a highly vertical etching slope along both the S/D and Wg directions. The fabricated Lg=60nm MBCFET showed a record combination of S=76mV/dec, gm-max=13.7 mS/mum, ION=2.24mA/mum and Q=180 at VDS=0.5V.

AB - In this paper, we report scalable 5 -level stacked gate-all-around (GAA) In 0.53 Ga0.47As multi-bridge channel FETs (MBCFETs), with careful attention paid to fluorine migration. At its heart, we maintained temperature of all the unit process steps below 300 °C and inserted an n-InP ledge into a top In0.52Al0.48As sacrificial layer to suppress F- -induced donor passivation. In addition, we used a selectively regrown n+In0.53Ga0.47 As contact formation by MOCVD and precision dry etching. The dry etching process resulted in a highly vertical etching slope along both the S/D and Wg directions. The fabricated Lg=60nm MBCFET showed a record combination of S=76mV/dec, gm-max=13.7 mS/mum, ION=2.24mA/mum and Q=180 at VDS=0.5V.

UR - https://www.scopus.com/pages/publications/85167621998

U2 - 10.23919/VLSITechnologyandCir57934.2023.10185250

DO - 10.23919/VLSITechnologyandCir57934.2023.10185250

M3 - Conference contribution

AN - SCOPUS:85167621998

T3 - Digest of Technical Papers - Symposium on VLSI Technology

BT - 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 11 June 2023 through 16 June 2023

ER -

Yoo JH, Jo HB, Lee IG, Choi SM, Baek JM, Lee ST et al. L_g= 60 nm In_0.53Ga_0.47As MBCFETs: From g_m-max= 13.7 mS/μm and Q = 180 to virtual-source modeling. In 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.23919/VLSITechnologyandCir57934.2023.10185250