TY - GEN
T1 - Memory-efficient architecture for contrast enhancement and integral image computation
AU - Kim, Dongsub
AU - Hyun, Jongkil
AU - Moon, Byungin
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/1
Y1 - 2020/1
N2 - This paper proposes a hardware architecture for contrast-limited adaptive histogram equalization (CLAHE) and integral image computation, focusing on the efficient use of memory resources. To save memory resources, the proposed architecture processes each pixel entered in real time without storing the entire image. In addition, this architecture improves resource utilization by optimizing the tile size of CLAHE and computing the integral image via an adder tree. When the proposed architecture was implemented in Xilinx's FPGA XC7Z045 FFG900-2, it used 98, 945 slice LUTs, 85, 600 slice registers, and 8 BRAMs for the CLAHE module, and it used 7, 834 slice LUTs, 7, 498 slice registers, and 19 BRAMs for the integral image module. In addition, the proposed architecture operated at a maximum frequency of 129 MHz in 512 × 512 image resolution.
AB - This paper proposes a hardware architecture for contrast-limited adaptive histogram equalization (CLAHE) and integral image computation, focusing on the efficient use of memory resources. To save memory resources, the proposed architecture processes each pixel entered in real time without storing the entire image. In addition, this architecture improves resource utilization by optimizing the tile size of CLAHE and computing the integral image via an adder tree. When the proposed architecture was implemented in Xilinx's FPGA XC7Z045 FFG900-2, it used 98, 945 slice LUTs, 85, 600 slice registers, and 8 BRAMs for the CLAHE module, and it used 7, 834 slice LUTs, 7, 498 slice registers, and 19 BRAMs for the integral image module. In addition, the proposed architecture operated at a maximum frequency of 129 MHz in 512 × 512 image resolution.
KW - CLAHE
KW - Face detection
KW - FPGA
KW - Hardware architecture
KW - Integral image
UR - http://www.scopus.com/inward/record.url?scp=85083492073&partnerID=8YFLogxK
U2 - 10.1109/ICEIC49074.2020.9051296
DO - 10.1109/ICEIC49074.2020.9051296
M3 - Conference contribution
AN - SCOPUS:85083492073
T3 - 2020 International Conference on Electronics, Information, and Communication, ICEIC 2020
BT - 2020 International Conference on Electronics, Information, and Communication, ICEIC 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2020 International Conference on Electronics, Information, and Communication, ICEIC 2020
Y2 - 19 January 2020 through 22 January 2020
ER -