Minimizing redundancy-based motion estimation design for high-definition

Jeong Hoon Kim; In Jung Lyu; Hyun June Lyu; Jun Rim Choi

doi:10.1109/VLSISoC.2011.6081662

Minimizing redundancy-based motion estimation design for high-definition

Jeong Hoon Kim, In Jung Lyu, Hyun June Lyu, Jun Rim Choi

School of Electronics Engineering

Kyungpook National University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, the redundant data in integer motion estimation that comes from overlapping reference blocks of consecutive current macro blocks processing is eliminated to reduce memory access rate. Based on early predicted candidate in fractional motion estimation, unique interpolation processing is employed to reduce the latency by half. In addition, based on high correlation, the scheme of processing 4x8 and 4x4 block with free of cycles is proposed, so that the number of motion vectors on FME can be reduced up to 59%. Experimental results show that the proposed motion estimation design saves 16% of gate count and 65% of local memory while supporting higher encoding specification.

Original language	English
Title of host publication	2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011
Pages	110-113
Number of pages	4
DOIs	https://doi.org/10.1109/VLSISoC.2011.6081662
State	Published - 2011
Event	2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011 - Kowloon, Hong Kong Duration: 3 Oct 2011 → 5 Oct 2011

Publication series

Name	2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011

Conference

Conference	2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011
Country/Territory	Hong Kong
City	Kowloon
Period	3/10/11 → 5/10/11

Keywords

H.264/AVC
motion estimation
video signal processing
VLSI architecture

Access to Document

10.1109/VLSISoC.2011.6081662

Cite this

Kim, J. H., Lyu, I. J., Lyu, H. J., & Choi, J. R. (2011). Minimizing redundancy-based motion estimation design for high-definition. In 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011 (pp. 110-113). Article 6081662 (2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011). https://doi.org/10.1109/VLSISoC.2011.6081662

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title = "Minimizing redundancy-based motion estimation design for high-definition",

abstract = "In this paper, the redundant data in integer motion estimation that comes from overlapping reference blocks of consecutive current macro blocks processing is eliminated to reduce memory access rate. Based on early predicted candidate in fractional motion estimation, unique interpolation processing is employed to reduce the latency by half. In addition, based on high correlation, the scheme of processing 4x8 and 4x4 block with free of cycles is proposed, so that the number of motion vectors on FME can be reduced up to 59%. Experimental results show that the proposed motion estimation design saves 16% of gate count and 65% of local memory while supporting higher encoding specification.",

keywords = "H.264/AVC, motion estimation, video signal processing, VLSI architecture",

author = "Kim, {Jeong Hoon} and Lyu, {In Jung} and Lyu, {Hyun June} and Choi, {Jun Rim}",

year = "2011",

doi = "10.1109/VLSISoC.2011.6081662",

language = "English",

isbn = "9781457701719",

series = "2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011",

pages = "110--113",

booktitle = "2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011",

note = "2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011 ; Conference date: 03-10-2011 Through 05-10-2011",

}

Kim, JH, Lyu, IJ, Lyu, HJ & Choi, JR 2011, Minimizing redundancy-based motion estimation design for high-definition. in 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011., 6081662, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, pp. 110-113, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, Kowloon, Hong Kong, 3/10/11. https://doi.org/10.1109/VLSISoC.2011.6081662

Minimizing redundancy-based motion estimation design for high-definition. / Kim, Jeong Hoon; Lyu, In Jung; Lyu, Hyun June et al.
2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011. 2011. p. 110-113 6081662 (2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Minimizing redundancy-based motion estimation design for high-definition

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