Modified reset waveform to widen driving margin under low address voltage in AC-plasma display panel

This paper proposes a new reset driving waveform to widen the driving margin under a low address voltage in AC-PDPs. The proposed reset waveform alters the wall charge distribution between the X-Y electrodes by applying an X-ramp bias prior to an address-period, thereby lowering the minimum level of the scan pulse (ΔV_y) during an address-period without any misfiring discharge in the off-cells. Whenadopting the proposed reset waveform, the address discharge time delay is reduced by about 200ns at an address voltage of 35V, while the related dynamic driving margin is wide under a low address voltage condition. The related phenomena are also examined using the V _t close-curve method.