Modified two-step SOVA-based turbo decoder with a fixed scaling factor

Dae Won Kim; Taek Won Kwon; Jun Rim Choi; Jun Jin Kong

doi:10.1109/ISCAS.2000.858682

Modified two-step SOVA-based turbo decoder with a fixed scaling factor

Dae Won Kim, Taek Won Kwon, Jun Rim Choi, Jun Jin Kong

School of Electronics Engineering

Kyungpook National University

Research output: Contribution to journal › Conference article › peer-review

21 Scopus citations

Abstract

In this paper, two optimum implementation schemes are proposed in soft output Viterbi algorithm (SOVA) with high performance. One is modifying the architecture known as two-step SOVA scheme in order to obtain high speed. The other is lowering the reliability values to a same level with a scaling factor 0.25 or 0.33 for hardware implementation in order to compensate for the distortion. Also, we have implemented one step SOVA and the modified architecture for comparison of two schemes with 0.65 um Samsung SOG technology using verilog HDL. At result, The modified architecture provides higher SNR performance by 2 dB at the BER 1E-04 than that of the general SOVA. Also we have obtained good performance by using a fixed scaling factor, by which the soft output of SOVA can be considered as being multiplied. The simulation results show that the modified architecture with both methods contributes to high performance.

Original language	English
Pages (from-to)	IV-37-IV-40
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	4
DOIs	https://doi.org/10.1109/ISCAS.2000.858682
State	Published - 2000
Event	Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000 - Geneva, Switz, Switzerland Duration: 28 May 2000 → 31 May 2000

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10.1109/ISCAS.2000.858682

Cite this

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title = "Modified two-step SOVA-based turbo decoder with a fixed scaling factor",

abstract = "In this paper, two optimum implementation schemes are proposed in soft output Viterbi algorithm (SOVA) with high performance. One is modifying the architecture known as two-step SOVA scheme in order to obtain high speed. The other is lowering the reliability values to a same level with a scaling factor 0.25 or 0.33 for hardware implementation in order to compensate for the distortion. Also, we have implemented one step SOVA and the modified architecture for comparison of two schemes with 0.65 um Samsung SOG technology using verilog HDL. At result, The modified architecture provides higher SNR performance by 2 dB at the BER 1E-04 than that of the general SOVA. Also we have obtained good performance by using a fixed scaling factor, by which the soft output of SOVA can be considered as being multiplied. The simulation results show that the modified architecture with both methods contributes to high performance.",

author = "Kim, {Dae Won} and Kwon, {Taek Won} and Choi, {Jun Rim} and Kong, {Jun Jin}",

year = "2000",

doi = "10.1109/ISCAS.2000.858682",

language = "English",

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pages = "IV--37--IV--40",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000 ; Conference date: 28-05-2000 Through 31-05-2000",

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T1 - Modified two-step SOVA-based turbo decoder with a fixed scaling factor

AU - Kim, Dae Won

AU - Kwon, Taek Won

AU - Choi, Jun Rim

AU - Kong, Jun Jin

PY - 2000

Y1 - 2000

N2 - In this paper, two optimum implementation schemes are proposed in soft output Viterbi algorithm (SOVA) with high performance. One is modifying the architecture known as two-step SOVA scheme in order to obtain high speed. The other is lowering the reliability values to a same level with a scaling factor 0.25 or 0.33 for hardware implementation in order to compensate for the distortion. Also, we have implemented one step SOVA and the modified architecture for comparison of two schemes with 0.65 um Samsung SOG technology using verilog HDL. At result, The modified architecture provides higher SNR performance by 2 dB at the BER 1E-04 than that of the general SOVA. Also we have obtained good performance by using a fixed scaling factor, by which the soft output of SOVA can be considered as being multiplied. The simulation results show that the modified architecture with both methods contributes to high performance.

AB - In this paper, two optimum implementation schemes are proposed in soft output Viterbi algorithm (SOVA) with high performance. One is modifying the architecture known as two-step SOVA scheme in order to obtain high speed. The other is lowering the reliability values to a same level with a scaling factor 0.25 or 0.33 for hardware implementation in order to compensate for the distortion. Also, we have implemented one step SOVA and the modified architecture for comparison of two schemes with 0.65 um Samsung SOG technology using verilog HDL. At result, The modified architecture provides higher SNR performance by 2 dB at the BER 1E-04 than that of the general SOVA. Also we have obtained good performance by using a fixed scaling factor, by which the soft output of SOVA can be considered as being multiplied. The simulation results show that the modified architecture with both methods contributes to high performance.

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DO - 10.1109/ISCAS.2000.858682

M3 - Conference article

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JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000

Y2 - 28 May 2000 through 31 May 2000

ER -

Modified two-step SOVA-based turbo decoder with a fixed scaling factor

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