@inproceedings{7a4aba6842ec4c73a356ec77ed483c2e,
title = "Multi-threshold voltages graphene barristor-based ternary ALU",
abstract = "Ternary logic circuits can provide simpler circuit structure and a significant reduction in power consumption via reduced interconnects. We propose a signed ternary arithmetic logic unit (ALU) which is designed with multi-threshold voltages graphene barristors. We simulated the ternary logic circuits using SPICE model of an experimentally proven multi-threshold voltages graphene barristor. Our proposed ternary ALU demonstrates improved energy-efficiency compared to the binary design; 87% and 93% reduction of power-delay product in the 5-trit ternary adder-subtractor and ternary multiplier, respectively.",
keywords = "Graphene barristor, Multiple-valued logic, Ternary ALU, Ternary logic",
author = "Sunghye Park and Sunmean Kim and Seokhyeong Kang",
note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 16th International System-on-Chip Design Conference, ISOCC 2019 ; Conference date: 06-10-2019 Through 09-10-2019",
year = "2019",
month = oct,
doi = "10.1109/ISOCC47750.2019.9078492",
language = "English",
series = "Proceedings - 2019 International SoC Design Conference, ISOCC 2019",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "25--26",
booktitle = "Proceedings - 2019 International SoC Design Conference, ISOCC 2019",
address = "United States",
}