Multi-threshold voltages graphene barristor-based ternary ALU

Sunghye Park, Sunmean Kim, Seokhyeong Kang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Ternary logic circuits can provide simpler circuit structure and a significant reduction in power consumption via reduced interconnects. We propose a signed ternary arithmetic logic unit (ALU) which is designed with multi-threshold voltages graphene barristors. We simulated the ternary logic circuits using SPICE model of an experimentally proven multi-threshold voltages graphene barristor. Our proposed ternary ALU demonstrates improved energy-efficiency compared to the binary design; 87% and 93% reduction of power-delay product in the 5-trit ternary adder-subtractor and ternary multiplier, respectively.

Original languageEnglish
Title of host publicationProceedings - 2019 International SoC Design Conference, ISOCC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages25-26
Number of pages2
ISBN (Electronic)9781728124780
DOIs
StatePublished - Oct 2019
Event16th International System-on-Chip Design Conference, ISOCC 2019 - Jeju, Korea, Republic of
Duration: 6 Oct 20199 Oct 2019

Publication series

NameProceedings - 2019 International SoC Design Conference, ISOCC 2019
Volume2019-January

Conference

Conference16th International System-on-Chip Design Conference, ISOCC 2019
Country/TerritoryKorea, Republic of
CityJeju
Period6/10/199/10/19

Keywords

  • Graphene barristor
  • Multiple-valued logic
  • Ternary ALU
  • Ternary logic

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