Multi-threshold voltages graphene barristor-based ternary ALU

Sunghye Park; Sunmean Kim; Seokhyeong Kang

doi:10.1109/ISOCC47750.2019.9078492

Multi-threshold voltages graphene barristor-based ternary ALU

Sunghye Park
, Sunmean Kim
, Seokhyeong Kang

School of Electronics Engineering

Pohang University of Science and Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

Ternary logic circuits can provide simpler circuit structure and a significant reduction in power consumption via reduced interconnects. We propose a signed ternary arithmetic logic unit (ALU) which is designed with multi-threshold voltages graphene barristors. We simulated the ternary logic circuits using SPICE model of an experimentally proven multi-threshold voltages graphene barristor. Our proposed ternary ALU demonstrates improved energy-efficiency compared to the binary design; 87% and 93% reduction of power-delay product in the 5-trit ternary adder-subtractor and ternary multiplier, respectively.

Original language	English
Title of host publication	Proceedings - 2019 International SoC Design Conference, ISOCC 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	25-26
Number of pages	2
ISBN (Electronic)	9781728124780
DOIs	https://doi.org/10.1109/ISOCC47750.2019.9078492
State	Published - Oct 2019
Event	16th International System-on-Chip Design Conference, ISOCC 2019 - Jeju, Korea, Republic of Duration: 6 Oct 2019 → 9 Oct 2019

Publication series

Name	Proceedings - 2019 International SoC Design Conference, ISOCC 2019
Volume	2019-January

Conference

Conference	16th International System-on-Chip Design Conference, ISOCC 2019
Country/Territory	Korea, Republic of
City	Jeju
Period	6/10/19 → 9/10/19

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Graphene barristor
Multiple-valued logic
Ternary ALU
Ternary logic

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10.1109/ISOCC47750.2019.9078492

Cite this

Park, S., Kim, S., & Kang, S. (2019). Multi-threshold voltages graphene barristor-based ternary ALU. In Proceedings - 2019 International SoC Design Conference, ISOCC 2019 (pp. 25-26). Article 9078492 (Proceedings - 2019 International SoC Design Conference, ISOCC 2019; Vol. 2019-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC47750.2019.9078492

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title = "Multi-threshold voltages graphene barristor-based ternary ALU",

abstract = "Ternary logic circuits can provide simpler circuit structure and a significant reduction in power consumption via reduced interconnects. We propose a signed ternary arithmetic logic unit (ALU) which is designed with multi-threshold voltages graphene barristors. We simulated the ternary logic circuits using SPICE model of an experimentally proven multi-threshold voltages graphene barristor. Our proposed ternary ALU demonstrates improved energy-efficiency compared to the binary design; 87\% and 93\% reduction of power-delay product in the 5-trit ternary adder-subtractor and ternary multiplier, respectively.",

keywords = "Graphene barristor, Multiple-valued logic, Ternary ALU, Ternary logic",

author = "Sunghye Park and Sunmean Kim and Seokhyeong Kang",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 16th International System-on-Chip Design Conference, ISOCC 2019 ; Conference date: 06-10-2019 Through 09-10-2019",

year = "2019",

month = oct,

doi = "10.1109/ISOCC47750.2019.9078492",

language = "English",

series = "Proceedings - 2019 International SoC Design Conference, ISOCC 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "25--26",

booktitle = "Proceedings - 2019 International SoC Design Conference, ISOCC 2019",

address = "United States",

}

Park, S, Kim, S & Kang, S 2019, Multi-threshold voltages graphene barristor-based ternary ALU. in Proceedings - 2019 International SoC Design Conference, ISOCC 2019., 9078492, Proceedings - 2019 International SoC Design Conference, ISOCC 2019, vol. 2019-January, Institute of Electrical and Electronics Engineers Inc., pp. 25-26, 16th International System-on-Chip Design Conference, ISOCC 2019, Jeju, Korea, Republic of, 6/10/19. https://doi.org/10.1109/ISOCC47750.2019.9078492

Multi-threshold voltages graphene barristor-based ternary ALU. / Park, Sunghye; Kim, Sunmean; Kang, Seokhyeong.
Proceedings - 2019 International SoC Design Conference, ISOCC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 25-26 9078492 (Proceedings - 2019 International SoC Design Conference, ISOCC 2019; Vol. 2019-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Multi-threshold voltages graphene barristor-based ternary ALU

AU - Park, Sunghye

AU - Kim, Sunmean

AU - Kang, Seokhyeong

PY - 2019/10

Y1 - 2019/10

N2 - Ternary logic circuits can provide simpler circuit structure and a significant reduction in power consumption via reduced interconnects. We propose a signed ternary arithmetic logic unit (ALU) which is designed with multi-threshold voltages graphene barristors. We simulated the ternary logic circuits using SPICE model of an experimentally proven multi-threshold voltages graphene barristor. Our proposed ternary ALU demonstrates improved energy-efficiency compared to the binary design; 87% and 93% reduction of power-delay product in the 5-trit ternary adder-subtractor and ternary multiplier, respectively.

AB - Ternary logic circuits can provide simpler circuit structure and a significant reduction in power consumption via reduced interconnects. We propose a signed ternary arithmetic logic unit (ALU) which is designed with multi-threshold voltages graphene barristors. We simulated the ternary logic circuits using SPICE model of an experimentally proven multi-threshold voltages graphene barristor. Our proposed ternary ALU demonstrates improved energy-efficiency compared to the binary design; 87% and 93% reduction of power-delay product in the 5-trit ternary adder-subtractor and ternary multiplier, respectively.

KW - Graphene barristor

KW - Multiple-valued logic

KW - Ternary ALU

KW - Ternary logic

UR - https://www.scopus.com/pages/publications/85113861799

U2 - 10.1109/ISOCC47750.2019.9078492

DO - 10.1109/ISOCC47750.2019.9078492

M3 - Conference contribution

AN - SCOPUS:85113861799

T3 - Proceedings - 2019 International SoC Design Conference, ISOCC 2019

SP - 25

EP - 26

BT - Proceedings - 2019 International SoC Design Conference, ISOCC 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 16th International System-on-Chip Design Conference, ISOCC 2019

Y2 - 6 October 2019 through 9 October 2019

ER -

Multi-threshold voltages graphene barristor-based ternary ALU

Abstract

Publication series

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UN SDGs

Keywords

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