New systolic modular multiplication architecture for efficient montgomery multiplication

Se Hyu Choi, Keon Jik Lee

Research output: Contribution to journalArticlepeer-review

9 Scopus citations

Abstract

We propose a new low complexity Montgomery algorithm enabling the efficient selection of the quotient value necessary for an exact division in Montgomery multiplication. We also present two new systolic multipliers which use similar data flows as described in the most significant bit (MSB)-first GF(2m) multiplier in [1]. The proposed parallel and serial multipliers have less hardware and time complexities compared to related multiplier. The serial multiplier can be well applied to space-limited hardware. Furthermore, our proposed systolic multipliers include regularity, modularity, local interconnection, and unidirectional data flow features.

Original languageEnglish
Article number20141051
JournalIEICE Electronics Express
Volume12
Issue number2
DOIs
StatePublished - 26 Dec 2015

Keywords

  • Modular multiplication
  • Montgomery
  • Systolic array

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