Abstract
The radio frequency (RF) model of SOI FinFETs with gate length of 40 nm is verified by using a 3-dimensional (3-D) device simulator. This paper shows the equivalent circuit model which can be used in the circuit analysis simulator. The RMS modeling error of Y-parameter was calculated to be only 0.3%.
| Original language | English |
|---|---|
| Pages (from-to) | 160-164 |
| Number of pages | 5 |
| Journal | Journal of Semiconductor Technology and Science |
| Volume | 10 |
| Issue number | 2 |
| DOIs | |
| State | Published - 2010 |
Keywords
- Model
- Model verification
- Parameter extraction
- Radio frequency
- Soi finfet