Abstract
We proposed for the first time a new double-gate 1T-DRAM cell to be applicable to sub-80-nm DRAM technology that has a silicon-oxidenitride- oxidesilicon type storage node on the back gate (control gate) for nonvolatile memory (NVM) functionality. An NVM functionality is achieved by FowlerNordheim tunneling of electrons into the nitride storage node. Then, holes are accumulated on the back-channel, which makes 1T-DRAM operation in fully depleted silicon-on-insulator (SOI) MOSFETs possible and enhances retention characteristics. We investigated the effect of the NVM functionality on 1T-DRAM performance in nanoscale 1T-DRAM cells through device simulation and verified the effect in 0.6-μm devices fabricated on SOI wafers.
Original language | English |
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Article number | 5409557 |
Pages (from-to) | 614-619 |
Number of pages | 6 |
Journal | IEEE Transactions on Electron Devices |
Volume | 57 |
Issue number | 3 |
DOIs | |
State | Published - Mar 2010 |
Keywords
- 1T-DRAM
- Capacitorless DRAM
- Double-gate (DG) MOSFET
- Embedded memory
- Floating-body effect
- Nonvolatile
- Silicon-on-insulator (SOI) MOSFETs