@inproceedings{3ca7b5e140084f5889429940c46272f9,
title = "NS3K: A 3nm nanosheet FET library for VLSI prediction in advanced nodes",
abstract = "Nanosheet FETs (NSFETs) are expected as future devices that replace FinFETs beyond the 5nm node. Despite the importance of the devices, few studies report the impact of NSFETs in the full-chip level. Therefore, this paper presents NS3K, the first 3nm NSFET library, and presents the results in a full-chip scale. Based on our results, 3nm NSFET reduces power by -27.4%, total wirelength by -25.8%, number of cells by -8.5%, and area by -47.6% over 5nm FinFET, respectively, due to better devices and interconnect scaling. However, careful device/layout designs followed by routing-resource considering standard cells are required to maximize the advantages of 3nm technology.",
keywords = "FinFET, Library, NSFET, Standard cell",
author = "Taehak Kim and Jaehoon Jeong and Seungmin Woo and Jeonggyu Yang and Hyunwoo Kim and Ahyeon Nam and Changdong Lee and Jinmin Seo and Minji Kim and Siwon Ryu and Yoonju Oh and Taigon Song",
note = "Publisher Copyright: {\textcopyright} 2021 IEEE; 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 ; Conference date: 22-05-2021 Through 28-05-2021",
year = "2021",
doi = "10.1109/ISCAS51556.2021.9401055",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings",
address = "United States",
}