@inproceedings{ee37e75fb62e4bc583917d530242c377,
title = "Optimization of GAA vertical nanowire performance for logic application",
abstract = "In this work, we analyze the vertical GaN nanowire and investigate its logic performance and improvement through 3D simulation. The trapping effects are well analyzed and the curves are closely fitted to the experimental work. Further, this work suggested some methods to improve the logic performances by including the effect of m-plane side walls and optimizing the effects of dimension reduction. The performances improvement can be seen by the significant reduction in DIBL upto 40mV/V and SS upto 65 mV/dec.",
keywords = "3D simulation, component, GaN vertical nanowire, logic, TCAD",
author = "Terirama Thingujam and Son, {Dong Hyeok} and Kim, {Jeong Gil} and Lee, {Yong Soo} and Kang, {In Man} and Lee, {Jung Hee}",
note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019 ; Conference date: 01-04-2019 Through 03-04-2019",
year = "2019",
month = apr,
doi = "10.1109/EUROSOI-ULIS45800.2019.9041873",
language = "English",
series = "2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019",
address = "United States",
}