Optimizing Ternary Multiplier Design With Fast Ternary Adder

Existing ternary multiplier designs are difficult to use in ternary systems. Thus, ternary Wallace tree multipliers that reduce the number of transistors by using 4-input ternary adders are proposed to improve the performance of existing ternary multipliers. A ternary carry-select adder is also proposed to reduce the carry propagation delay, used as a carry-chain adder of the Wallace tree. The proposed multipliers are designed with a custom ternary standard cell library synthesized by multi-threshold complementary metal-oxide-semiconductor (CMOS) with a 28~nm process. Power and delay are verified via HSPICE simulation. The proposed 36\times36 ternary multiplier shows 79.3% power-delay product improvement over the previous ternary multiplier. The proposed 40\times40 ternary multiplier shows a power-delay product comparable with that of the 64\times64 binary multiplier synthesized using Synopsys Design Compiler.