Parallel in/out systolic AB2 architecture with low complexity in GF(2m)

S. H. Choi; K. J. Lee

doi:10.1049/el.2015.3681

Parallel in/out systolic AB² architecture with low complexity in GF(2^m)

S. H. Choi
, K. J. Lee

Department of Civil Engineering

Kyungpook National University

Research output: Contribution to journal › Article › peer-review

2 Scopus citations

Abstract

Efficient GF(2^mm) arithmetic clearly affects the performance of compute-intensive applications. A new low-complexity parallel-in/ out systolic AB²multiplier based on the least significant bit-first scheme is presented. Compared with related works, the scheme yields significantly lower area-time complexity.

Original language	English
Pages (from-to)	1138-1140
Number of pages	3
Journal	Electronics Letters
Volume	52
Issue number	13
DOIs	https://doi.org/10.1049/el.2015.3681
State	Published - 23 Jun 2016

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title = "Parallel in/out systolic AB2 architecture with low complexity in GF(2m)",

abstract = "Efficient GF(2mm) arithmetic clearly affects the performance of compute-intensive applications. A new low-complexity parallel-in/ out systolic AB2multiplier based on the least significant bit-first scheme is presented. Compared with related works, the scheme yields significantly lower area-time complexity.",

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AB - Efficient GF(2mm) arithmetic clearly affects the performance of compute-intensive applications. A new low-complexity parallel-in/ out systolic AB2multiplier based on the least significant bit-first scheme is presented. Compared with related works, the scheme yields significantly lower area-time complexity.

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JO - Electronics Letters

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Parallel in/out systolic AB² architecture with low complexity in GF(2^m)

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