Parallel in/out systolic AB2 architecture with low complexity in GF(2m)

S. H. Choi; K. J. Lee

doi:10.1049/el.2015.3681

Parallel in/out systolic AB² architecture with low complexity in GF(2^m)

S. H. Choi, K. J. Lee

Department of Civil Engineering

Kyungpook National University

Research output: Contribution to journal › Article › peer-review

2 Scopus citations

Abstract

Efficient GF(2^mm) arithmetic clearly affects the performance of compute-intensive applications. A new low-complexity parallel-in/ out systolic AB²multiplier based on the least significant bit-first scheme is presented. Compared with related works, the scheme yields significantly lower area-time complexity.

Original language	English
Pages (from-to)	1138-1140
Number of pages	3
Journal	Electronics Letters
Volume	52
Issue number	13
DOIs	https://doi.org/10.1049/el.2015.3681
State	Published - 23 Jun 2016

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@article{1d61948cd3304ef68bd48ca24ad82854,

title = "Parallel in/out systolic AB2 architecture with low complexity in GF(2m)",

abstract = "Efficient GF(2mm) arithmetic clearly affects the performance of compute-intensive applications. A new low-complexity parallel-in/ out systolic AB2multiplier based on the least significant bit-first scheme is presented. Compared with related works, the scheme yields significantly lower area-time complexity.",

author = "Choi, \{S. H.\} and Lee, \{K. J.\}",

note = "Publisher Copyright: {\textcopyright} The Institution of Engineering and Technology 2016.",

year = "2016",

month = jun,

day = "23",

doi = "10.1049/el.2015.3681",

language = "English",

volume = "52",

pages = "1138--1140",

journal = "Electronics Letters",

issn = "0013-5194",

publisher = "John Wiley \& Sons Inc.",

number = "13",

}

TY - JOUR

T1 - Parallel in/out systolic AB2 architecture with low complexity in GF(2m)

AU - Choi, S. H.

AU - Lee, K. J.

N1 - Publisher Copyright: © The Institution of Engineering and Technology 2016.

PY - 2016/6/23

Y1 - 2016/6/23

N2 - Efficient GF(2mm) arithmetic clearly affects the performance of compute-intensive applications. A new low-complexity parallel-in/ out systolic AB2multiplier based on the least significant bit-first scheme is presented. Compared with related works, the scheme yields significantly lower area-time complexity.

AB - Efficient GF(2mm) arithmetic clearly affects the performance of compute-intensive applications. A new low-complexity parallel-in/ out systolic AB2multiplier based on the least significant bit-first scheme is presented. Compared with related works, the scheme yields significantly lower area-time complexity.

UR - https://www.scopus.com/pages/publications/84975062060

U2 - 10.1049/el.2015.3681

DO - 10.1049/el.2015.3681

M3 - Article

AN - SCOPUS:84975062060

SN - 0013-5194

VL - 52

SP - 1138

EP - 1140

JO - Electronics Letters

JF - Electronics Letters

IS - 13

ER -

Parallel in/out systolic AB² architecture with low complexity in GF(2^m)

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