Parallel reconfigurable computing and its application to hidden Markov model

A. Paul, Yung Chuan Jiang, Jechang Jeong

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

Parallel processing techniques are increasingly found in reconfigurable computing, especially in digital signal processing (DSP) applications. In this paper, we design a parallel reconfigurable computing (PRC) architecture which consists of multiple dynamically reconfigurable computing units. The hidden Markov model (HMM) algorithm is mapped onto the PRC architecture. First, we construct a directed acyclic graph (DAG) to represent the HMM algorithms. A novel parallel partition approach is then proposed to map the HMM DAG onto the multiple DRC units in a PRC system. This partitioning algorithm is capable of design optimization of parallel processing reconfigurable systems for a given number of processing elements in different HHM states.

Original languageEnglish
Title of host publicationIET International Conference on Frontier Computing. Theory, Technologies and Applications
Pages82-91
Number of pages10
Edition568 CP
DOIs
StatePublished - 2010
EventIET International Conference on Frontier Computing. Theory, Technologies and Applications - Taichung, Taiwan, Province of China
Duration: 4 Aug 20106 Aug 2010

Publication series

NameIET Conference Publications
Number568 CP
Volume2010

Conference

ConferenceIET International Conference on Frontier Computing. Theory, Technologies and Applications
Country/TerritoryTaiwan, Province of China
CityTaichung
Period4/08/106/08/10

Keywords

  • FPGA
  • HMM
  • parallel processors
  • partitioning algorithm
  • reconfigurable processing

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