Parallel simulation-assisted on-chip glitch filter placement for safe microcontroller in noisy environment

A chip-level fault propagation modeling and parallel simulation method is proposed to investigate efficiently glitch-weak lines of clock distributed networks. The cells of the chip are represented as stochastic and rulebased agent models that reproduce the phenomena of fault delivery to neighbor cells when a glitch is generated on the connected clock lines. To reduce simulation time to support checking the glitch tolerance of all clock lines and Monte Carlo simulation, cell agents are computed in parallel utilizing multi-cores to reduce single simulation time. The proposed method is applied to a target micro-controller to identify the glitch-weak lines and show the results of the physical glitch tolerance experiment after placing glitch filters on the candidate lines.