Parasitic extraction for heterogeneous face-to-face bonded 3-D ICs

Face-to-face (F2F)-bonded 3-D ICs provide higher vertical interconnection densities and cost-effective solutions compared to face-to-back-bonded 3-D ICs. With a bumpless direct-copper-bonding process, the die-to-die distance is significantly reduced to enable a finer F2F via pitch. Unfortunately, this increases interdie parasitic components that require careful extraction. Heterogeneous 3-D ICs are built using dies from different design houses and foundries, potentially using different technology nodes. They again require accurate parasitic extraction across multiple dies and thus call for new computer-aided design methodologies with intellectual property protection. We, for the first time, provide a comprehensive study of three full-chip parasitic extraction methods for homogeneous and heterogeneous F2F 3-D ICs. The traditional die-by-die extraction ignores any interdie coupling and underestimates the total coupling capacitance by 35%. The holistic extraction that takes all dies into account provides the most accurate results at the cost of high layout-versus-schematic (LVS) complexity. The in-context extraction, taking only the interface layers from the neighbor dies, offers tradeoffs between accuracy and complexity. Our study shows that with only two interface layers, in-context extraction offers highly accurate and efficient extraction results with 0.9% error for the total ground capacitance and 0.8% for the total coupling capacitance.