Performance analysis of ultra-scaled InAs HEMTs

Neerav Kharche; Gerhard Klimeck; Dae Hyun Kim; Jesús A. Del Alamo; Mathieu Luisier

doi:10.1109/IEDM.2009.5424315

Performance analysis of ultra-scaled InAs HEMTs

Neerav Kharche, Gerhard Klimeck, Dae Hyun Kim, Jesús A. Del Alamo, Mathieu Luisier

School of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

20 Scopus citations

Abstract

The scaling behavior of ultra-scaled InAs HEMTs is investigated using a 2-dimensional real-space effective mass ballistic quantum transport simulator. The simulation methodology is first benchmarked against experimental I _d-V_gs data obtained from devices with gate lengths ranging from 30 to 50 nm, where a good quantitative match is obtained. It is then applied to optimize the logic performance of not-yetfabricated 20nm InAs HEMT. It is demonstrated that the best performance is achieved in thin InAs channel devices by reducing the insulator thickness to improve the gate control while increasing the gate work function to suppress the gate leakage.

Original language	English
Title of host publication	2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest
Pages	20.3.1-20.3.4
DOIs	https://doi.org/10.1109/IEDM.2009.5424315
State	Published - 2009
Event	2009 International Electron Devices Meeting, IEDM 2009 - Baltimore, MD, United States Duration: 7 Dec 2009 → 9 Dec 2009

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Conference

Conference	2009 International Electron Devices Meeting, IEDM 2009
Country/Territory	United States
City	Baltimore, MD
Period	7/12/09 → 9/12/09

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10.1109/IEDM.2009.5424315

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@inproceedings{23c35cdebd814cd99d43bac8fedf0661,

title = "Performance analysis of ultra-scaled InAs HEMTs",

abstract = "The scaling behavior of ultra-scaled InAs HEMTs is investigated using a 2-dimensional real-space effective mass ballistic quantum transport simulator. The simulation methodology is first benchmarked against experimental I d-Vgs data obtained from devices with gate lengths ranging from 30 to 50 nm, where a good quantitative match is obtained. It is then applied to optimize the logic performance of not-yetfabricated 20nm InAs HEMT. It is demonstrated that the best performance is achieved in thin InAs channel devices by reducing the insulator thickness to improve the gate control while increasing the gate work function to suppress the gate leakage.",

author = "Neerav Kharche and Gerhard Klimeck and Kim, \{Dae Hyun\} and \{Del Alamo\}, \{Jes{\'u}s A.\} and Mathieu Luisier",

year = "2009",

doi = "10.1109/IEDM.2009.5424315",

language = "English",

isbn = "9781424456406",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

pages = "20.3.1--20.3.4",

booktitle = "2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest",

note = "2009 International Electron Devices Meeting, IEDM 2009 ; Conference date: 07-12-2009 Through 09-12-2009",

}

Kharche, N, Klimeck, G, Kim, DH, Del Alamo, JA & Luisier, M 2009, Performance analysis of ultra-scaled InAs HEMTs. in 2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest., 5424315, Technical Digest - International Electron Devices Meeting, IEDM, pp. 20.3.1-20.3.4, 2009 International Electron Devices Meeting, IEDM 2009, Baltimore, MD, United States, 7/12/09. https://doi.org/10.1109/IEDM.2009.5424315

Performance analysis of ultra-scaled InAs HEMTs. / Kharche, Neerav; Klimeck, Gerhard; Kim, Dae Hyun et al.
2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest. 2009. p. 20.3.1-20.3.4 5424315 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Performance analysis of ultra-scaled InAs HEMTs

AU - Kharche, Neerav

AU - Klimeck, Gerhard

AU - Kim, Dae Hyun

AU - Del Alamo, Jesús A.

AU - Luisier, Mathieu

PY - 2009

Y1 - 2009

N2 - The scaling behavior of ultra-scaled InAs HEMTs is investigated using a 2-dimensional real-space effective mass ballistic quantum transport simulator. The simulation methodology is first benchmarked against experimental I d-Vgs data obtained from devices with gate lengths ranging from 30 to 50 nm, where a good quantitative match is obtained. It is then applied to optimize the logic performance of not-yetfabricated 20nm InAs HEMT. It is demonstrated that the best performance is achieved in thin InAs channel devices by reducing the insulator thickness to improve the gate control while increasing the gate work function to suppress the gate leakage.

AB - The scaling behavior of ultra-scaled InAs HEMTs is investigated using a 2-dimensional real-space effective mass ballistic quantum transport simulator. The simulation methodology is first benchmarked against experimental I d-Vgs data obtained from devices with gate lengths ranging from 30 to 50 nm, where a good quantitative match is obtained. It is then applied to optimize the logic performance of not-yetfabricated 20nm InAs HEMT. It is demonstrated that the best performance is achieved in thin InAs channel devices by reducing the insulator thickness to improve the gate control while increasing the gate work function to suppress the gate leakage.

UR - https://www.scopus.com/pages/publications/77952324482

U2 - 10.1109/IEDM.2009.5424315

DO - 10.1109/IEDM.2009.5424315

M3 - Conference contribution

AN - SCOPUS:77952324482

SN - 9781424456406

T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 20.3.1-20.3.4

BT - 2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest

T2 - 2009 International Electron Devices Meeting, IEDM 2009

Y2 - 7 December 2009 through 9 December 2009

ER -

Performance analysis of ultra-scaled InAs HEMTs

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