Performance evaluation of 50 nm in0.7Ga0.3As HEMTs for beyond-CMOS logic applications

Dae Hyun Kim; Jesus A. Del Alamo; Jae Hak Lee; Kwang Seok Seo

Performance evaluation of 50 nm in_0.7Ga_0.3As HEMTs for beyond-CMOS logic applications

Dae Hyun Kim, Jesus A. Del Alamo, Jae Hak Lee, Kwang Seok Seo

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

62 Scopus citations

Abstract

We have studied the suitability of nanometer-scale In_0.7Ga _0.3As HEMTs as a high-speed, low-power logic technology for beyond-CMOS applications. To this end, we have fabricated 50-150 nm gate length In_0.7Ga_0.3As HEMTs with different gate stack designs. The 50 nm HEMTs exhibit I_ON/I_OFF ratios in excess of 10 ⁵ and DIBL less than 90 mV/dec. Compared with state-of-the-art Si MOSFET's, the non-optimized 50 nm In_0.7Ga_0.3As HEMTs provide equivalent highspeed performance with 15 times lower DC power dissipation and at least 2.7 times higher f_T at equivalent power dissipation level. In the landscape of alternatives for beyond CMOS technologies, InAs-rich InGaAs HEMTs hold considerable promise.

Original language	English
Title of host publication	IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest
Pages	767-770
Number of pages	4
State	Published - 2005
Event	IEEE International Electron Devices Meeting, 2005 IEDM - Washington, DC, MD, United States Duration: 5 Dec 2005 → 7 Dec 2005

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
Volume	2005
ISSN (Print)	0163-1918

Conference

Conference	IEEE International Electron Devices Meeting, 2005 IEDM
Country/Territory	United States
City	Washington, DC, MD
Period	5/12/05 → 7/12/05

Cite this

@inproceedings{1e95c35ed6554beeb421404793c8e0ff,

title = "Performance evaluation of 50 nm in0.7Ga0.3As HEMTs for beyond-CMOS logic applications",

abstract = "We have studied the suitability of nanometer-scale In0.7Ga 0.3As HEMTs as a high-speed, low-power logic technology for beyond-CMOS applications. To this end, we have fabricated 50-150 nm gate length In0.7Ga0.3As HEMTs with different gate stack designs. The 50 nm HEMTs exhibit ION/IOFF ratios in excess of 10 5 and DIBL less than 90 mV/dec. Compared with state-of-the-art Si MOSFET's, the non-optimized 50 nm In0.7Ga0.3As HEMTs provide equivalent highspeed performance with 15 times lower DC power dissipation and at least 2.7 times higher fT at equivalent power dissipation level. In the landscape of alternatives for beyond CMOS technologies, InAs-rich InGaAs HEMTs hold considerable promise.",

author = "Kim, {Dae Hyun} and {Del Alamo}, {Jesus A.} and Lee, {Jae Hak} and Seo, {Kwang Seok}",

year = "2005",

language = "English",

isbn = "078039268X",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

pages = "767--770",

booktitle = "IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest",

note = "IEEE International Electron Devices Meeting, 2005 IEDM ; Conference date: 05-12-2005 Through 07-12-2005",

}

Kim, DH, Del Alamo, JA, Lee, JH & Seo, KS 2005, Performance evaluation of 50 nm in_0.7Ga_0.3As HEMTs for beyond-CMOS logic applications. in IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest., 1609467, Technical Digest - International Electron Devices Meeting, IEDM, vol. 2005, pp. 767-770, IEEE International Electron Devices Meeting, 2005 IEDM, Washington, DC, MD, United States, 5/12/05.

Performance evaluation of 50 nm in_0.7Ga_0.3As HEMTs for beyond-CMOS logic applications. / Kim, Dae Hyun; Del Alamo, Jesus A.; Lee, Jae Hak et al.
IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest. 2005. p. 767-770 1609467 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Performance evaluation of 50 nm in0.7Ga0.3As HEMTs for beyond-CMOS logic applications

AU - Kim, Dae Hyun

AU - Del Alamo, Jesus A.

AU - Lee, Jae Hak

AU - Seo, Kwang Seok

PY - 2005

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N2 - We have studied the suitability of nanometer-scale In0.7Ga 0.3As HEMTs as a high-speed, low-power logic technology for beyond-CMOS applications. To this end, we have fabricated 50-150 nm gate length In0.7Ga0.3As HEMTs with different gate stack designs. The 50 nm HEMTs exhibit ION/IOFF ratios in excess of 10 5 and DIBL less than 90 mV/dec. Compared with state-of-the-art Si MOSFET's, the non-optimized 50 nm In0.7Ga0.3As HEMTs provide equivalent highspeed performance with 15 times lower DC power dissipation and at least 2.7 times higher fT at equivalent power dissipation level. In the landscape of alternatives for beyond CMOS technologies, InAs-rich InGaAs HEMTs hold considerable promise.

AB - We have studied the suitability of nanometer-scale In0.7Ga 0.3As HEMTs as a high-speed, low-power logic technology for beyond-CMOS applications. To this end, we have fabricated 50-150 nm gate length In0.7Ga0.3As HEMTs with different gate stack designs. The 50 nm HEMTs exhibit ION/IOFF ratios in excess of 10 5 and DIBL less than 90 mV/dec. Compared with state-of-the-art Si MOSFET's, the non-optimized 50 nm In0.7Ga0.3As HEMTs provide equivalent highspeed performance with 15 times lower DC power dissipation and at least 2.7 times higher fT at equivalent power dissipation level. In the landscape of alternatives for beyond CMOS technologies, InAs-rich InGaAs HEMTs hold considerable promise.

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M3 - Conference contribution

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T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 767

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BT - IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest

T2 - IEEE International Electron Devices Meeting, 2005 IEDM

Y2 - 5 December 2005 through 7 December 2005

ER -

Performance evaluation of 50 nm in_0.7Ga_0.3As HEMTs for beyond-CMOS logic applications

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